By default, the ADAU1381 is in I2C mode, but c" />
參數(shù)資料
型號(hào)： ADAU1381BCPZ-RL
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 30/84頁(yè)
文件大小： 0K
描述： IC AUDIO CODEC STEREO LN 32LFCSP
標(biāo)準(zhǔn)包裝： 5,000
類(lèi)型： 立體聲音頻
數(shù)據(jù)接口： 串行，SPI?
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無(wú)
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 97 / 100
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 96.5 / 100
電壓 - 電源，模擬： 1.8 V ~ 3.65 V
電壓 - 電源，數(shù)字： 1.63 V ~ 3.65 V
工作溫度： -25°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 帶卷 (TR)
配用： EVAL-ADAU1381Z-ND - BOARD EVALUATION FOR ADAU1381
ADAU1381
Rev. B | Page 36 of 84
SPI PORT
By default, the ADAU1381 is in I2C mode, but can be put into SPI
control mode by pulling CLATCH low three times. The SPI port
uses a 4-wire interface, consisting of CLATCH, CCLK, CDATA,
and COUT signals, and is always a slave port. The CLATCH signal
goes low at the beginning of a transaction and high at the end of
a transaction. The CCLK signal latches CDATA on a low-to-high
transition. COUT data is shifted out of the ADAU1381 on the
falling edge of CCLK and should be clocked into a receiving
device, such as a microcontroller, on the CCLK rising edge. The
CDATA signal carries the serial input data, and the COUT signal is
the serial output data. The COUT signal remains three-stated until
a read operation is requested. This allows other SPI-compatible
peripherals to share the same readback line. All SPI transactions
have the same basic format shown in
. A timing diagram
is shown in
. All data should be written MSB first. The
ADAU1381 can be taken out of SPI mode only by a full reset.
Chip Address R/W
The first byte of an SPI transaction includes the 7-bit chip address
and an R/W bit. The chip address is always 0x38. The LSB of
this first byte determines whether the SPI transaction is a read
(Logic 1) or a write (Logic 0).
Table 23. SPI Address Byte Format
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0
R/W
Subaddress
The 12-bit subaddress word is decoded into a location in one of
the registers. This subaddress is the location of the appropriate
register. The MSBs of the subaddress are zero-padded to bring the
word to a full 2-byte length.
Data Bytes
The number of data bytes varies according to the register being
accessed. During a burst mode write, an initial subaddress is
written followed by a continuous sequence of data for consecutive
register locations. A sample timing diagram for a single-write
SPI operation to the parameter memory is shown in Figure 44.
A sample timing diagram of a single-read SPI operation is shown in
Figure 45. The COUT pin goes from three-state to being driven at
the beginning of Byte 3. In this example, Byte 0 to Byte 2 contain
the addresses and R/W bit, and subsequent bytes carry the data.
SPI Read/Write Clock Frequency (CCLK)
The SPI port of the ADAU1381 has asymmetrical read and
write clock frequencies. It is possible to write data into the
device at higher data rates than reading data out of the device.
More detailed information is available in the Digital Timing
MEMORY AND REGISTER ACCESS
Several conditions must be true to have full access to all memory
and registers via the control port:
The ADAU1381 must have finished its initialization,
including power-on reset, PLL lock, and self-boot.
The core clock must be enabled (Register 16384 (0x4000),
clock control, Bit 0, core clock enable, set to 1).
The memory controller must be powered (Register 16512
(0x4080), Digital Power-Down 0, Bit 6, memory controller, set
to 1).
The sound engine must be powered (Register 16512 (0x4080),
Digital Power-Down 0, Bit 0, sound engine, set to 1).
Table 24. Generic Control Word Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 41
CHIP_ADR[6:0], R/W
SUBADR[15:8]
SUBADR[7:0]
Data
1 Continues to end of data.
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