f/X INPUT DIVIDE 1, 2, 3, 4 f × (R + N/M) I" />
參數(shù)資料
型號(hào)： ADAU1381BCPZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/84頁(yè)
文件大?。?/td> 0K
描述： IC AUDIO CODEC STEREO LN 32LFCSP
標(biāo)準(zhǔn)包裝： 5,000
類型： 立體聲音頻
數(shù)據(jù)接口： 串行，SPI?
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 97 / 100
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 96.5 / 100
電壓 - 電源，模擬： 1.8 V ~ 3.65 V
電壓 - 電源，數(shù)字： 1.63 V ~ 3.65 V
工作溫度： -25°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 帶卷 (TR)
配用： EVAL-ADAU1381Z-ND - BOARD EVALUATION FOR ADAU1381
ADAU1381
Rev. B | Page 27 of 84
CLOCKING AND SAMPLING RATES
f/X
INPUT DIVIDE
1, 2, 3, 4
f × (R + N/M)
INTEGER, NUMERATOR,
DENOMINATOR
INPUT MASTER
CLOCK FREQUENCY
256 ×
fS, 512 × fS,
768 ×
fS, 1024 × fS
MCKI
PLL CONTROL
CLOCK CONTROL
AUTOMATICALLY SET TO 1024 ×
fS
WHEN PLL CLOCK SOURCE SELECTED
ADCs
DACs
fS/
0.5, 1, 1.5, 2, 3, 4, 6
SOUND ENGINE
FRAME RATE
SOUND
ENGINE
fS/
0.5, 1, 1.5, 2, 3, 4, 6
CONVERTER
SAMPLING RATE
fS/
0.5, 1, 1.5, 2, 3, 4, 6
SERIAL PORT
SAMPLING RATE
SERIAL DATA
INPUT/OUTPUT
PORTS
A
DC_S
D
A
T
A/
G
P
IO
1
BC
L
K
/G
P
IO
2
L
RCL
K/
G
P
IO
3
D
AC_S
D
A
T
A/
G
P
IO
0
CORE
CLOCK
08
31
3-
02
7
Figure 29. Clock Routing Diagram
CORE CLOCK
For example, if the input to Bit 3 = 49.152 MHz (from PLL),
then Bits[2:1] = 1024 × fS; therefore,
The core clock divider generates a core clock either from the
PLL or directly from MCLK and can be set in Register 16384
(0x4000), clock control.
fS = 49.152 MHz/1024 = 48 kHz
Table 13. Clock Control Register (Register 16384, 0x4000)
Bits
Bit Name
The core clock is always in 256 × fS mode. Direct MCLK fre-
quencies must correspond to a value listed in Table 12, where fS
is the base sampling frequency. PLL outputs are always in 1024
× fS mode, and the clock control register automatically sets the
core clock divider to f/4 when using the PLL.
Settings
3
Clock source select
0: direct from MCKI pin (default)
1: PLL clock
[2:1]
Input master clock
frequency
00: 256 × fS (default)
01: 512 × fS
10: 768 × fS
11: 1024 × fS
Table 12. Core Clock Frequency Dividers
Input Clock Rate
Core Clock Divider
Core Clock
0
Core clock enable
0: core clock disabled (default)
1: core clock enabled
256 × fS
f/1
256 × fS
512 × fS
f/2
SAMPLING RATES
768 × fS
f/3
1024 × fS
f/4
The ADCs, DACs, and serial port share a common sampling
rate that is set in Register 16407 (0x4017), Converter Control 0.
Bits[2:0], converter sampling rate, set the sampling rate as a ratio of
the base sampling frequency. The sound engine sampling rate is
set in Register 16619 (0x40EB), sound engine frame rate, Bits[3:0],
sound engine frame rate, and the serial port sampling rate is set
in Register 16632 (0x40F8), serial port sampling rate, Bits[2:0],
serial port control sampling rate.
Clocks for the converters, the serial ports, and the sound engine are
derived from the core clock. The core clock can be derived directly
from MCLK, or it can be generated by the PLL. Register 16384
(0x4000), clock control, Bit 3, clock source select, determines
the clock source.
Bits[2:1], input master clock frequency, should be set according
to the expected input clock rate selected by Bit 3, clock source
select. The clock source select value also determines the core
clock rate and the base sampling frequency, fS.
It is strongly recommended that the sampling rates for the
converters, serial ports, and sound engine be set to the same
value, unless appropriate compensation filtering is done within
the sound engine.
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