參數(shù)資料
型號(hào): ADAU1381BCPZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 58/84頁
文件大小: 0K
描述: IC AUDIO CODEC STEREO LN 32LFCSP
標(biāo)準(zhǔn)包裝: 5,000
類型: 立體聲音頻
數(shù)據(jù)接口: 串行,SPI?
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 97 / 100
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 96.5 / 100
電壓 - 電源,模擬: 1.8 V ~ 3.65 V
電壓 - 電源,數(shù)字: 1.63 V ~ 3.65 V
工作溫度: -25°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ
包裝: 帶卷 (TR)
配用: EVAL-ADAU1381Z-ND - BOARD EVALUATION FOR ADAU1381
ADAU1381
Rev. B | Page 61 of 84
Register 16409 (0x4019), ADC Control
Bit 6, Invert Input Polarity
This bit enables an optional polarity inverter in the ADC path,
which is an amplifier with a gain of 1, representing a 180°
phase shift.
Bit 5, High-Pass Filter Select
This bit enables an optional high-pass filter in the ADC path,
with a cutoff frequency of 2 Hz when fS = 48 kHz. The cutoff
frequency scales linearly with fS.
Bit 4, Digital Microphone Data Polarity Swap
This bit inverts the polarity of valid data states for the digital
microphone data stream. A typical PDM microphone can drive
its data output pin either high or low, not both. This bit must be
configured accordingly to recognize a valid output state of the
microphone. The default is negative, meaning that a digital
logic low signal is recognized by the ADAU1381 as a pulse in
the PDM signal.
Bit 3, Digital Microphone Channel Swap
This bit allows the left and right channels of the digital microphone
input to swap. Standard mode is the left channel on the rising
edge and the right channel on the falling edge. Swapped mode is
the right channel on the rising edge and the left channel on the
falling edge.
Bit 2, Digital Microphone Input Select
This bit must be enabled in order to use the digital microphone
inputs. When this bit is asserted, the on-chip ADCs are off, BCLK
is the master at 128 × fS, and ADC_SDATA is expected to have
the left and right channels interleaved. This bit must be disabled
to use the ADCs.
Bits[1:0], ADC Enable
These bits must be configured to use the ADCs. ADC channels
can be enabled or disabled individually.
Table 44. ADC Control Register
Bits
Description
Default
7
Reserved
6
Invert input polarity
0
0: normal
1: inverted
5
High-pass filter select
0
0: disabled
1: enabled
4
Digital microphone data polarity swap
0
0: negative
1: positive
3
Digital microphone channel swap
0
0: standard mode
1: swapped mode
2
Digital microphone input select
0
0: digital microphone input off
1: select digital microphone input, ADCs off
[1:0]
ADC enable
00
00: both off
01: left on
10: right on
11: both on
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