參數(shù)資料
型號: ADAU1381BCPZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 63/84頁
文件大小: 0K
描述: IC AUDIO CODEC STEREO LN 32LFCSP
標準包裝: 5,000
類型: 立體聲音頻
數(shù)據(jù)接口: 串行,SPI?
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標準 ADC / DAC (db): 97 / 100
動態(tài)范圍,標準 ADC / DAC (db): 96.5 / 100
電壓 - 電源,模擬: 1.8 V ~ 3.65 V
電壓 - 電源,數(shù)字: 1.63 V ~ 3.65 V
工作溫度: -25°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應商設備封裝: 32-LFCSP-VQ
包裝: 帶卷 (TR)
配用: EVAL-ADAU1381Z-ND - BOARD EVALUATION FOR ADAU1381
ADAU1381
Rev. B | Page 66 of 84
Register 16423 (0x4027), Playback Speaker Output
Control
Bits[7:6], Speaker Output Gain Control
These bits control the gain of the speaker output. In general, this
parameter should be tuned at a system level, set once during system
initialization and not altered during operation of the system.
Bit 0, Speaker Output Enable
This bit enables the speaker output. It initiates the speaker power-
up and power-down sequences shown in Figure 36 and Figure 37.
Register 16424 (0x4028), Beep Zero-Crossing Detector
Control
Bits[4:3], Detector Timeout
The timeout detector waits the specified amount of time for a
beep zero crossing before forcing the mute or unmute in the
playback path beep gains (that is, the left playback beep gain,
right playback beep gain, and mono playback beep gain).
Bit 0, Zero-Crossing Detector Enable
This bit enables the zero-crossing detector. Disabling the beep
zero-crossing detector may cause clicks and pops on the output
when using the beep path.
Table 53. Playback Speaker Output Control Register
Bits
Description
Default
[7:6]
Speaker output gain control
00
00: 0 dB
01: 2 dB
10: 4 dB
11: 6 dB
[5:1]
Reserved
0
Speaker output enable
0
0: disabled
1: enabled
Table 54. Beep Zero-Crossing Detector Control Register
Bits
Description
Default
[7:5]
Reserved
[4:3]
Detector timeout
11
00: 20 ms
01: 10 ms
10: 5 ms
11: 2.5 ms
[2:1]
Reserved
0
Zero-crossing detector enable
1
0: disabled
1: enabled
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