參數(shù)資料
型號(hào)： AD9980KSTZ-95
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 35/44頁(yè)
文件大小： 0K
描述： IC INTERFACE 8BIT ANALOG 80LQFP
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： 視頻
接口： 模擬
電源電壓： 3.13 V ~ 3.47 V
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 管件
安裝類型： 表面貼裝
配用： AD9980/PCBZ-ND - KIT EVALUATION AD9980
AD9980
Rev. 0 | Page 40 of 44
PCB LAYOUT RECOMMENDATIONS
The AD9980 is a high-precision, high-speed analog device.
To achieve the maximum performance from the part, it is
important to have a well laid-out board. The Analog Interface
Inputs section contains a guide for designing a board using
the AD9980.
Analog Interface Inputs
Using the following layout techniques on the graphics inputs is
extremely important:
1.
Minimize the trace length running into the graphics inputs.
This is accomplished by placing the AD9980 as close as
possible to the graphics VGA connector. Long input trace
lengths are undesirable because they pick up noise from
the board and other external sources.
2.
Place the 75 termination resistors (see Figure 3) as close
as possible to the AD9980 chip. Any additional trace length
between the termination resistors and the input of the
AD9980 increases the magnitude of reflections, which
corrupts the graphics signal.
3.
Use 75 matched impedance traces. Trace impedances
other than 75 also increases the chance of reflections.
4.
The AD9980 has very high input bandwidth (200 MHz).
While this is desirable for acquiring a high resolution PC
graphics signal with fast edges, it also means that it
captures any high frequency noise present. Therefore, it is
important to reduce the amount of noise that gets coupled
to the inputs. Avoid running any digital traces near the
analog inputs.
5.
Due to the high bandwidth of the AD9980, sometimes
low-pass filtering the analog inputs can help to reduce
noise. (For many applications, filtering is unnecessary.)
Experiments have shown that placing a ferrite bead in
series prior to the 75 termination resistor is helpful in
filtering excess noise. Specifically, the Fair-Rite
#2508051217Z0 was used, but an application could work
best with a different bead value. Alternatively, placing a
100 to 120 resistor between the 75 termination
resistor and the input coupling capacitor is beneficial.
Power Supply Bypassing
It is recommended to bypass each power supply pin with a
0.1 F capacitor. The exception is where two or more supply
pins are adjacent to each other. For these groupings of
powers/grounds, it is only necessary to have one bypass
capacitor. The fundamental idea is to have a bypass capacitor
within about 0.5 cm of each power pin. Also, avoid placing the
capacitor on the opposite side of the PC board from the
AD9980, since that interposes resistive vias in the path.
The bypass capacitors should be physically located between the
power plane and the power pin. Current should flow from the
power plane > capacitor > power pin. Do not make the power
connection between the capacitor and the power pin. Placing a
via underneath the capacitor pads, down to the power plane, is
generally the best approach.
It is particularly important to maintain low noise and good
stability of PVD (the clock generator supply). Abrupt changes in
PVD can result in similarly abrupt changes in sampling clock
phase and frequency. This can be avoided by careful attention to
regulation, filtering, and bypassing. It is highly desirable to
provide separate regulated supplies for each of the analog
circuitry groups (VD and PVD).
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog
supply regulator, which in turn can produce changes in the
regulated analog supply voltage. This can be mitigated by
regulating the analog supply, or at least PVD, from a different,
cleaner, power source (for example, from a 12 V supply).
It is also recommended to use a single ground plane for the
entire board. Experience has repeatedly shown that the noise
performance is the same or better with a single ground plane.
Using multiple ground planes can be detrimental because each
separate ground plane is smaller and long ground loops can
result.
In some cases, using separate ground planes is unavoidable. For
those cases, it is recommended to at least place a single ground
plane under the AD9980. The location of the split should be at
the receiver of the digital outputs. In this case, it is even more
important to place components wisely because the current
loops will be much longer (current takes the path of least
resistance). An example of a current loop is power plane to
AD9980 to digital output trace to digital data receiver to digital
ground plane to analog ground plane.
PLL
Place the PLL loop filter components as close to the FILT pin as
possible. Do not place any digital or other high frequency traces
near these components. Use the values suggested in the data-
sheet with 10% tolerances or less.
Outputs (Both Data and Clocks)
Try to minimize the trace length that the digital outputs have to
drive. Longer traces have higher capacitance and require more
instantaneous current to drive, which creates more internal
digital noise. Shorter traces reduce the possibility of reflections.
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