參數(shù)資料
型號： AD9980KSTZ-95
廠商： Analog Devices Inc
文件頁數(shù)： 25/44頁
文件大小： 0K
描述： IC INTERFACE 8BIT ANALOG 80LQFP
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： 視頻
接口： 模擬
電源電壓： 3.13 V ~ 3.47 V
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 管件
安裝類型： 表面貼裝
配用： AD9980/PCBZ-ND - KIT EVALUATION AD9980
AD9980
Rev. 0 | Page 31 of 44
0x14
4
Input Vsync Polarity
If Bit 5 of Register 0x14 is 1, the value of this bit
specifies the polarity of the input Vsync. Setting this
bit to 0 indicates an active low Vsync; setting this bit to
1 indicates an active high Vsync. Power-up default is 1.
Table 24. Vsync Input Polarity Settings
Override Bit
Result
0
Vsync input polarity is negative
1
Vsync input polarity is positive
0x14
3
Vsync Output Polarity
This bit sets the polarity of the Hsync output. Setting
this bit to 0 sets the Hsync output to active low. Setting
this bit to 1 sets the Hsync output to active high.
Power-up default is 1.
Table 25. Vsync Output Polarity Settings
Vsync Output
Polarity Bit
Result
0
Vsync output polarity is negative
1
Vsync output polarity is positive
0x14
2
Vsync Filter Enable
This bit enables the Vsync filter allowing precise
placement of the Vsync with respect to the Hsync
and facilitating the correct operation of the
Hsyncs/Vsync count.
Table 26. Vsync Filter Enable
Vsync Filter Bit
Result
0
Vsync filter disabled
1
Vsync filter enabled
0x14
1
Vsync Duration Enable
This enables the Vsync duration block, which is
designed to be used with the Vsync filter. Setting the
bit to 0 leaves the Vsync output duration unchanged.
Setting the bit to 1 sets the Vsync output duration
based on Register 0x15. Power-up duration is 0.
Table 27. Vsync Duration Enable
Vsync
Duration Bit
Result
0
Vsync output duration is unchanged
1
Vsync output duration is set by Register 0x15
0x15
7:0
Vsync Duration
This is used to set the output duration of the Vsync,
and is designed to be used with the Vsync filter. This is
valid only if Register 0x14, Bit 1 is set to 1. Power-up
default is 10.
COAST AND CLAMP CONTROLS
0x16
7:0
Precoast
This register allows the internally generated Coast
signal to be applied prior to the Vsync signal. This is
necessary in cases where pre-equalization pulses are
present. The step size for this control is one Hsync
period. For Precoast to work correctly, it is necessary
for the Vsync filter (Register 0x14, Bit 2) and sync
processing filter (Register 0x20, Bit 1) both to be either
enabled or disabled. The power-up default is 00.
0x17
7:0
Postcoast
This register allows the internally generated Coast
signal to be applied following the Vsync signal. This is
necessary in cases where post equalization pulses are
present. The step size for this control is one Hsync
period. For Postcoast to work correctly, it is necessary
for the Vsync filter (Register 0x14, Bit 2) and sync
processing filter (Register 0x20, Bit 1) both to be either
enabled or disabled. The power-up default is 00.
0x18
7
Coast Source
This bit is used to select the active Coast source. The
choices are the COAST input pin or Vsync. If Vsync is
selected, the additional decision of using the Vsync
input pin or the output from the sync separator needs
to be made (Register 0x14, Bits [7: 6]).
Table 28. Coast Source Selection Settings
Select
Result
0
Vsync (internal Coast)
1
COAST input pin
0x18
6
Coast Polarity Override
This register is used to override the internal circuitry
that determines the polarity of the Coast signal going
into the PLL. The power-up default setting is 0.
Table 29. Coast Polarity Override Settings
Override Bit
Result
0
Coast polarity determined by chip
1
Coast polarity determined by user
0x18
5
Input Coast Polarity
This register sets the input Coast polarity when Bit 6
of Register 0x18 = 1. The power-up default setting is 1.
Table 30. Coast Polarity Settings
Coast Polarity
Bit
Result
0
Coast polarity is negative
1
Coast polarity is positive
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