參數(shù)資料
型號： AD9980KSTZ-95
廠商： Analog Devices Inc
文件頁數(shù)： 30/44頁
文件大?。?/td> 0K
描述： IC INTERFACE 8BIT ANALOG 80LQFP
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： 視頻
接口： 模擬
電源電壓： 3.13 V ~ 3.47 V
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 管件
安裝類型： 表面貼裝
配用： AD9980/PCBZ-ND - KIT EVALUATION AD9980
AD9980
Preliminary Technical Data
Rev. 0 | Page 36 of 44
DETECTION STATUS
0x24
7
Hsync0 Detection Bit
This bit is used to indicate when activity is detected on
the HSYNC0 input pin. If Hsync is held high or low,
activity will not be detected. The sync processing
block diagram shows where this function is imple-
mented. 0 = Hsync0 is not active. 1 = Hsync0 is active.
Table 60. Hsync0 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x24
6
Hsync1 Detection Bit
This bit is used to indicate when activity is detected on
the HSYNC1 input pin. If Hsync is held high or low,
activity is not detected. The sync processing block
diagram shows where this function is implemented.
0 = Hsync1 is not active. 1 = Hsync1 is active.
Table 61. Hsync1 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x24
5
Vsync0 Detection Bit
This bit is used to indicate when activity is detected on
the VSYNC0 input pin. If Vsync is held high or low,
activity is not detected. The sync processing block
diagram shows where this function is implemented.
0 = Vsync0 not active. 1 = Vsync0 is active.
Table 62. Vsync0 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x24
4
Vsync1 Detection Bit
This bit is used to indicate when activity is detected on
the Vsync1 input pin. If Vsync is held high or low,
activity is not detected. The sync processing block
diagram shows where this function is implemented.
0 = Vsync1 is not active, 1 = Vsync1 is active.
Table 63. Vsync1 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x24
3
SOG0 Detection Bit
This bit is used to indicate when activity is detected on
the SOG0 input pin. If SOG is held high or low,
activity is not detected. The sync processing block
diagram shows where this function is implemented.
0 = SOG0 is not active. 1 = SOG1 is active.
Table 64. SOG0 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x24
2
SOG1 Detection Bit
This bit is used to indicate when activity is detected on
the SOG1 input pin. If SOG is held high or low,
activity is not detected. The sync processing block
diagram shows where this function is implemented.
0 = SOG1 not active. 1 = SOG1 is active.
Table 65. SOG1 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x24
1
Coast Detection Bit
This bit detects activity on the EXTCLK/EXTCOAST
pin. It indicates one of the two signals is active, but it
won’t indicate if it is EXTCLK or EXTCOAST. A dc
signal is not detected.
Table 66. COAST Detection Result
Detect
Result
0
No activity detected
1
Activity detected
0x24
0
Clamp Detection Bit
This bit is used to indicate when activity is detected on
the external clamp pin. If external clamp is held high
or low, activity is not detected.
Table 67. Clamp Detection Results
Detect
Result
0
No activity detected
1
Activity detected
POLARITY STATUS
0x25
7
Hsync0 Polarity
Indicates the polarity of Hsync0 input.
Table 68. Detected Hsync0 Polarity Results
Detect
Result
0
Hsync polarity is negative
1
Hsync polarity is positive
0x25
6
Hsync1 Polarity
Indicates the polarity of Hsync1 input.
Table 69. Detected Hsync1 Polarity Results
Detect
Result
0
Hsync polarity is negative
1
Hsync polarity is positive
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