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參數(shù)資料
| 型號： | AD9980KSTZ-95 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE 8BIT ANALOG 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 應(yīng)用： | 視頻 |
| 接口： | 模擬 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
| 配用： | AD9980/PCBZ-ND - KIT EVALUATION AD9980 |
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AD9980
Preliminary Technical Data
Rev. 0 | Page 34 of 44
power-down to be controlled by software. With
manual power-down control, the polarity of the
power-down pin must be set (0x1E, Bit 2) whether it is
used or not. If unused, it is recommended to set the
polarity to active high and to hardwire the pin to
ground with a 10 k resistor.
Table 44. Auto Power-Down Select
Power-Down Select
Result
0
Manual power-down control
User determines power-down
1
Auto power-down control
Chip determines power-down
0x1E
3
Power-Down
This bit is used to manually put the chip in power-
down mode. It is used only if manual power-down
control is selected (see Bit 4 of the power-down
register). Both the state of this register bit and the
power-down pin (Pin 17) are used to control manual
power-down (see the Power Management section for
more details on power-down.).
Table 45. Power-Down Settings
Power-Down Select
Pin 17
Result
0
Normal operation
1
X
Power-down
0x1E
2
Power-Down Polarity
This bit defines the polarity of the power-down pin (Pin 17). It
is only used if manual power-down control is selected (see Bit 4
above).
Table 46. Power-Down Pin Polarity
Select
Result
0
Power-down pin is active low
1
Power-down pin is active high
0x1E
1
Power-Down Fast Switching Control
This bit controls a special fast switching mode. With
this bit, the AD9980 can stay active during power-
down and only put the outputs in high impedance.
This option is useful when the data outputs from two
chips are connected on a PCB and the user wants to
switch instantaneously between the two.
Table 47. Power-Down Fast Switching Control
Fast
Switching Control
Result
0
Normal power-down operation
1
The chip stays powered-up and the
outputs are put in high impedance
mode
0x1E
0
SOGOUT High Impedance Control
This bit controls whether the SOGOUT output pin is
in high impedance or not when in power-down mode.
In most cases, SOGOUT is not put in high impedance
during normal operation. It is usually needed for sync
detection by the graphics controller. The option to put
SOGOUT in high impedance is included mainly to
allow for factory testing modes.
Table 48. SOGOUT High Impedance Control
SOGOUT
Control
Result
0
The SOGOUT output operates as normal
during power-down.
1
The SOGOUT output is in high impedance
during power-down.
OUTPUT CONTROL
0x1F
6:5
Output Mode
These bits choose between three options for the
output mode. In 4:4:4 mode RGB is standard, in 4:2:2
mode YCbCr is standard, which allows a reduction in
the number of output pins from 24 to 16. In 4:4:4
DDR output mode, the data is in RGB mode but
changes on every clock edge. The power-up default
setting is 00.
Table 49. Output Mode
Output Mode
Result
00
4:4:4 RGB mode
01
4:2:2 YCbCr mode
10
4:4:4 DDR mode
0x1F
4
Primary Output Enable
This bit places the primary output in active or high
impedance mode. The power-up default setting is 1.
Table 50. Primary Output Enable
Select
Result
0
Primary output is in high impedance mode
1
Primary output is enabled
0x1F
3
Secondary Output Enable
This bit places the secondary output in active or high
impedance mode.
The secondary output is designated when using either
4:2:2 or 4:4:4 DDR. In these modes, the data on the
blue output channel is the secondary output while the
output data on the red and green channels are the
primary output. Secondary output is always a YCbCr
DDR data mode. See the Output Formatter section
and Table 11. The power-up default setting is 0.
Table 51. Secondary Output Enable
Select
Result
0
Secondary output is in high impedance mode
1
Secondary output is enabled
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