TMIN to TMA" />
參數(shù)資料
型號: AD9772AASTZRL
廠商: Analog Devices Inc
文件頁數(shù): 38/40頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 160MSPS 48LQFP
產(chǎn)品培訓(xùn)模塊: DAC Architectures
標(biāo)準(zhǔn)包裝: 2,000
系列: TxDAC+®
設(shè)置時間: 11ns
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 272mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 160M
AD9772A
Rev. C | Page 7 of 40
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 3.
Parameter
Min
Typ
Max
Unit
DIGITAL INPUTS
Logic 1 Voltage
2.1
3
V
Logic 0 Voltage
0
0.9
V
Logic 1 Current1
10
+10
μA
Logic 0 Current
10
+10
μA
Input Capacitance
5
pF
CLOCK INPUTS
Input Voltage Range
0
3
V
Common-Mode Voltage
0.75
1.5
2.25
V
Differential Voltage
0.5
1.5
V
PLL CLOCK ENABLED (SEE Figure 2)
Input Setup Time (tS)
TA = 25°C
1.5
ns
TA = 40 to +85°C
2.1
ns
Input Hold Time (tH)
TA = 25°C
1.3
ns
TA = 40 to +85°C
1.6
ns
Latch Pulse Width (tLPW), TA = 25°C
1.5
ns
PLL CLOCK DISABLED (SEE Figure 3)
Input Setup Time (tS)
TA = 25°C
0.7
ns
TA = 40 to +85°C
0.4
ns
Input Hold Time (tH)
TA = 25°C
3.3
ns
TA = 40 to +85°C
3.7
ns
Latch Pulse Width (tLPW), TA = 25°C
1.5
ns
CLK+/CLK to PLLLOCK Delay (tOD)
TA = 25°C
1.9
2.8
ns
TA = 40 to +85°C
1.8
3.3
ns
PLLLOCK (VOH), TA = 25°C
3.0
V
PLLLOCK (VOL), TA = 25°C
0.3
V
1 MOD0, MOD1, DIV0, DIV1, SLEEP, RESET have typical input currents of 15 μA.
tS
0.025%
DB0 TO DB13
CLK+ – CLK–
IOUTA
OR
IOUTB
tH
tLPW
tPD
tST
02
253
-00
2
Figure 2. Timing Diagram—PLL Clock Multiplier Enabled
tS
DB0 TO DB13
0.025%
IOUTA
OR
IOUTB
tOD
PLLLOCK
CLK+ – CLK–
t
H
tLPW
tPD
tST
02
25
3-
0
03
Figure 3. Timing Diagram—PLL Clock Multiplier Disabled
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