AD9772A
Rev. C | Page 7 of 40
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 3.
Parameter
Min
Typ
Max
Unit
DIGITAL INPUTS
Logic 1 Voltage
2.1
3
V
Logic 0 Voltage
0
0.9
V
10
+10
μA
Logic 0 Current
10
+10
μA
Input Capacitance
5
pF
CLOCK INPUTS
Input Voltage Range
0
3
V
Common-Mode Voltage
0.75
1.5
2.25
V
Differential Voltage
0.5
1.5
V
Input Setup Time (tS)
TA = 25°C
1.5
ns
TA = 40 to +85°C
2.1
ns
Input Hold Time (tH)
TA = 25°C
1.3
ns
TA = 40 to +85°C
1.6
ns
Latch Pulse Width (tLPW), TA = 25°C
1.5
ns
Input Setup Time (tS)
TA = 25°C
0.7
ns
TA = 40 to +85°C
0.4
ns
Input Hold Time (tH)
TA = 25°C
3.3
ns
TA = 40 to +85°C
3.7
ns
Latch Pulse Width (tLPW), TA = 25°C
1.5
ns
CLK+/CLK to PLLLOCK Delay (tOD)
TA = 25°C
1.9
2.8
ns
TA = 40 to +85°C
1.8
3.3
ns
PLLLOCK (VOH), TA = 25°C
3.0
V
PLLLOCK (VOL), TA = 25°C
0.3
V
1 MOD0, MOD1, DIV0, DIV1, SLEEP, RESET have typical input currents of 15 μA.
tS
0.025%
DB0 TO DB13
CLK+ – CLK–
IOUTA
OR
IOUTB
tH
tLPW
tPD
tST
02
253
-00
2
Figure 2. Timing Diagram—PLL Clock Multiplier Enabled
tS
DB0 TO DB13
0.025%
IOUTA
OR
IOUTB
tOD
PLLLOCK
CLK+ – CLK–
t
H
tLPW
tPD
tST
02
25
3-
0
03
Figure 3. Timing Diagram—PLL Clock Multiplier Disabled