TMIN to T
參數(shù)資料
型號: AD9772AASTZRL
廠商: Analog Devices Inc
文件頁數(shù): 39/40頁
文件大小: 0K
描述: IC DAC 14BIT 160MSPS 48LQFP
產品培訓模塊: DAC Architectures
標準包裝: 2,000
系列: TxDAC+®
設置時間: 11ns
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 272mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 160M
AD9772A
Rev. C | Page 8 of 40
DIGITAL FILTER SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, differential transformer-coupled output,
50 Ω doubly terminated, unless otherwise noted.
Table 4.
Parameter
Min
Typ
Max
Unit
MAXIMUM INPUT DATA RATE (fDATA)
150
MSPS
DIGITAL FILTER CHARACTERISTICS
Pass-Bandwidth1: 0.005 dB
0.401
fOUT/fDATA
Pass-Bandwidth: 0.01 dB
0.404
fOUT/fDATA
Pass-Bandwidth: 0.1 dB
0.422
fOUT/fDATA
Pass-Bandwidth: 3 dB
0.479
fOUT/fDATA
LINEAR PHASE (FIR IMPLEMENTATION)
STOP BAND REJECTION
73
dB
0.606 fCLOCK to 1.394 fCLOCK
11
Input clocks
GROUP DELAY2
IMPULSE RESPONSE DURATION
40 dB
36
Input clocks
60 dB
42
Input clocks
1 Excludes sin(x)/x characteristic of DAC.
2 Defined as the number of data clock cycles between impulse input and peak of output response.
FREQUENCY (DC TO
fDATA)
0
–140
0
1.0
0. 1
OU
T
P
U
T
(
d
B
)
0. 2
0.3
0. 4
0.5
0.6
0.7
0.8
0.9
–20
–40
–60
–80
–100
–120
0
2
253
-00
4
Figure 4. FIR Filter Frequency Response—Baseband Mode
TIME (Samples)
1.0
–0.4
0
5
NO
RM
AL
IZ
E
D
O
U
T
P
U
T
10
15
20
25
30
35
40
45
0.8
0.6
0.4
0.2
0
–0.2
022
53
-00
5
Figure 5. FIR Filter Impulse Response—Baseband Mode
Table 5. Integer Filter Coefficients for Interpolation Filter
(43-Tap Half-Band FIR Filter)
Lower
Coefficient
Upper
Coefficient
Integer
Value
H(1)
H(43)
10
H(2)
H(42)
0
H(3)
H(41)
31
H(4)
H(40)
0
H(5)
H(39)
69
H(6)
H(38)
0
H(7)
H(37)
138
H(8)
H(36)
0
H(9)
H(35)
248
H(10)
H(34)
0
H(11)
H(33)
419
H(12)
H(32)
0
H(13)
H(31)
678
H(14)
H(30)
0
H(15)
H(29)
1083
H(16)
H(28)
0
H(17)
H(27)
1776
H(18)
H(26)
0
H(19)
H(25)
3282
H(20)
H(24)
0
H(21)
H(23)
10,364
H(22)
16,384
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