參數(shù)資料
型號(hào)： AD9772AASTZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/40頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT 160MSPS 48LQFP
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 2,000
系列： TxDAC+®
設(shè)置時(shí)間： 11ns
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 272mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電流，單極；2 電流，雙極
采樣率（每秒）： 160M
AD9772A
Rev. C | Page 21 of 40
differential clock input should be driven with a reference clock
that is twice the data input rate in baseband applications, or that
is four times the data input rate in direct IF applications in
which the quarter-wave mixing option is employed (that is,
MOD1 and MOD0 active high). The clock distribution circuitry
remains enabled, providing a 1× internal clock at PLLLOCK.
Digital input data is latched into the AD9772A on every other
rising edge of the differential clock input. The rising edge that
corresponds to the input latch immediately precedes the rising
edge of the 1× clock at PLLLOCK. Adequate setup and hold
times for the input data, as shown in Figure 3, should be
allowed. Note that enough delay is present between
CLK+/CLK and the data input latch to cause the minimum
setup time for input data to be negative. This is noted in the
Digital Filter Specifications section. PLLLOCK contains a
relatively weak driver output, with its output delay (tOD)
sensitive to output capacitance loading. Therefore, PLLLOCK
should be buffered for fanouts greater than 1 and/or for load
capacitance greater than 10 pF. If a data timing issue exists
between the AD9772A and its external driver device, the
1× clock appearing at PLLLOCK can be inverted via an external
gate to ensure proper setup and hold time.
CHARGE
PUMP
PHASE
DETECTOR
EXT/INT
CLOCK CONTROL
PRESCALER
CLKVDD
OUT1×
CLKCOM
MOD1 MOD0 RESET
CLK+
LPF
PLLVDD
PLLCOM
DIV1
DIV0
CLOCK
DISTRIBUTION
–
+
PLLLOCK
CLK–
VCO
AD9772A
02
25
3-
03
3
Figure 33. Clock Multiplier with PLL Clock Multiplier Disabled
SYNCHRONIZATION OF CLOCK/DATA USING
RESET WITH PLL DISABLED
The relationship between the internal and external clocks in
this mode is shown in Figure 34. A clock at the output update
data rate (2× the input data rate) must be applied to the CLK+
and CLK inputs. Internal dividers create the internal 1× clock
necessary for the input latches. With the PLL disabled, a delayed
version of the 1× clock is present at the PLLLOCK pin. The
DAC latch is updated on the rising edge of the external 2× clock
that corresponds to the rising edge of the 1× clock. Updates to
the input data should be synchronized to this rising edge as
shown in Figure 34. To ensure this synchronization, a Logic 1
should be momentarily applied to the RESET pin on power-up
before CLK+/CLK is applied. Momentarily applying a Logic 1
to the RESET pin brings the 1× clock at PLLLOCK to a Logic 1.
On the next rising edge of the 2× clock, the 1× clock goes to
Logic 0. The following rising edge of the 2× clock causes the 1×
clock to go to Logic 1 again and updates the data in both of the
input latches.
DIGITAL DATA IN
EXTERNAL
2× CLOCK
DELAYED INTERNAL
1× CLOCK
LOAD-DEPENDENT,
DELAYED 1× CLOCK
AT PLLLOCK
IOUTA OR IOUTB
DATA
tLPW
tD
tPD
DATA ENTERS INPUT
LATCHES ON THIS EDGE
02
25
3-
03
4
Figure 34. Internal Timing of AD9772A with PLL Disabled
Figure 35 and Figure 36 illustrate the details of the RESET
function timing. The RESET pin going from a high to a low
logic level enables the 1× clock output generated by the
PLLLOCK pin. If RESET goes low before the rising edge of the
2× clock as shown in Figure 35, PLLLOCK goes high on the
following edge of the 2× clock. If RESET goes from a high to a
low logic level 600 ps or later following the rising edge of the 2×
clock, as shown in Figure 36, there is a delay of one 2× clock
cycle before PLLLOCK goes high. In either case, as long as
RESET remains low, PLLLOCK changes state on every rising
edge of the 2× clock. As previously stated, the rising edge of the
2× clock immediately preceding the rising edge of PLLLOCK
latches data into the AD9772A input latches.
[ T
]
1
2
3
T
CH1 2.00V CH2 2.00V M 10.0ns CH3 2.00V
T
EXTERNAL
1× CLOCK
PLLLOCK
RESET
02
25
3
-03
5
Figure 35. RESET Timing with PLL Disabled
[ T
]
1
2
3
T
CH1 2.00VV CH2 2.00VV M 10.0ns CH4
1.20V
CH3 2.00V
EXTERNAL
2× CLOCK
PLLLOCK
RESET
022
53
-036
Figure 36. RESET Timing with PLL Disabled and Insufficient Setup Time
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9772A-EB 制造商:Analog Devices 功能描述:14 BIT DAC W/2X INTERPOLATION 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9772A - Bulk
AD9772A-EBZ 功能描述:BOARD EVAL FOR AD9772A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
AD9772AST 制造商:Rochester Electronics LLC 功能描述:14 BIT DAC W/2X INTERPOLA - Tape and Reel
AD9772EB 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter
AD9773 制造商:AD 制造商全稱:Analog Devices 功能描述:Analog Devices: Data Converters: DAC 12-Bit, 10 ns to 100 ns Converters Selection Table
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