參數(shù)資料
型號(hào)： AD9772AASTZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 18/40頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT 160MSPS 48LQFP
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 2,000
系列： TxDAC+®
設(shè)置時(shí)間： 11ns
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 272mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸出數(shù)目和類(lèi)型： 2 電流，單極；2 電流，雙極
采樣率（每秒）： 160M
AD9772A
Rev. C | Page 25 of 40
AD9772A
CLK+
CLKVDD
CLK–
CLKCOM
0.1F
1k
ECL/PECL
0
22
53-
04
4
The power dissipation is directly proportional to the analog
supply current, IAVDD, and the digital supply current, IDVDD. IAVDD
is directly proportional to IOUTFS and is not sensitive to fDATA.
Conversely, IDVDD is dependent on both the digital input
waveform and fDATA. Figure 45 shows IDVDD as a function of full-
scale sine wave output ratios (fOUT/fDATA) for various update rates
with DVDD = 3.3 V. The supply current from CLKVDD and
PLLVDD is relatively insensitive to the digital input waveform
but directly proportional to the update rate, as shown in Figure 46.
Figure 44. Differential Clock Interface
RATIO (
fOUT/fDATA)
100
90
40
0
I DV
DD
(m
A
)
80
70
60
50
0.1
0.2
0.3
0.4
0.5
30
20
10
0
fDATA = 160MSPS
fDATA = 125MSPS
fDATA = 100MSPS
fDATA = 65MSPS
fDATA = 50MSPS
fDATA = 25MSPS
0
2
253
-045
The quality of the clock and data input signals is important in
achieving the optimum performance. The external clock driver
circuitry should provide the AD9772A with a low jitter clock
input, which meets the minimum/maximum logic levels while
providing fast edges. Although fast clock edges help minimize
jitter manifesting as phase noise on a reconstructed waveform,
the high gain-bandwidth product of the AD9772A differential
comparator can tolerate sine wave inputs as low as 0.5 V p-p,
with minimal degradation in its output noise floor.
Digital signal paths should be kept short, and run lengths
should match to avoid propagation delay mismatch. The
insertion of a low value resistor network (that is, 50 Ω to 200 Ω)
between the AD9772A digital inputs and driver outputs may be
helpful in reducing overshooting and ringing at the digital
inputs that contribute to data feedthrough.
Figure 45. IDVDD vs. Ratio @ DVDD = 3.3 V
fDATA (MSPS)
25
0
C
URRE
NT
(
m
A)
20
15
10
5
50
100
150
200
IPLLVDD
ICLKVDD
02
25
3
-04
6
SLEEP MODE OPERATION
The AD9772A has a sleep function that turns off the output current
and reduces the analog supply current to less than 6 mA over the
specified supply range of 3.1 V to 3.5 V. This mode can be activated
by applying a Logic Level 1 to the SLEEP pin. The AD9772A
takes less than 50 ns to power down and then approximately 15 μs
to power up.
POWER DISSIPATION
The power dissipation, PD, of the AD9772A is dependent on
several factors, including
The power supply voltages (AVDD, PLLVDD, CLKVDD,
and DVDD)
Figure 46. IPLLVDD and ICLKVDD vs. fDATA
The full-scale current output (IOUTFS)
The update rate (fDATA)
The reconstructed digital input waveform
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9772A-EB 制造商:Analog Devices 功能描述:14 BIT DAC W/2X INTERPOLATION 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9772A - Bulk
AD9772A-EBZ 功能描述:BOARD EVAL FOR AD9772A RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
AD9772AST 制造商:Rochester Electronics LLC 功能描述:14 BIT DAC W/2X INTERPOLA - Tape and Reel
AD9772EB 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter
AD9773 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Analog Devices: Data Converters: DAC 12-Bit, 10 ns to 100 ns Converters Selection Table
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