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參數(shù)資料
| 型號： | AD9772AASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 160MSPS 48LQFP |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | TxDAC+® |
| 設(shè)置時間： | 11ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 272mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 160M |
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AD9772A
Rev. C | Page 24 of 40
of the output stage and affect the reliability of the AD9772A.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. Operation beyond the
positive compliance range induces clipping of the output signal,
which severely degrades the AD9772A linearity and distortion
performance.
Operating the AD9772A with reduced voltage output swings
at IOUTA and IOUTB in a differential or single-ended output
configuration reduces the signal dependency of its output
impedance, thus enhancing distortion performance. Although
the voltage compliance range of IOUTA and IOUTB extends from
1.0 V to +1.25 V, optimum distortion performance is achieved
when the maximum full-scale signal at I
B
OUTA
and IOUTB
B
does not
exceed approximately 0.5 V. Using a properly selected
transformer with a grounded center tap allows the AD9772A to
provide the required power and voltage levels to different loads
while maintaining reduced voltage swings at IOUTA and IOUTB.
DC-coupled applications requiring a differential or single-
ended output configuration should size RLOAD accordingly. Refer
to the Output Configurations section for examples of various
output configurations.
The most significant improvement in the AD9772A distortion
and noise performance is realized using a differential output
configuration. The common-mode error sources of both IOUTA
and IOUTB can be substantially reduced by the common-mode
rejection of a transformer or differential amplifier. These
common-mode error sources include even-order distortion
products and noise. The enhancement in distortion performance
becomes more significant as the reconstructed waveform’s
frequency content increases and/or its amplitude decreases. The
distortion and noise performance of the AD9772A is also
dependent on the full-scale current setting, I
B
OUTFS
. Although IOUTFS
can be set between 2 mA and 20 mA, selecting an IOUTFS of 20 mA
provides the best distortion and noise performance.
In summary, the AD9772A achieves the optimum distortion
and noise performance under the following conditions:
Positive voltage swing at IOUTA and IOUTB limited to 0.5 V
B
Differential operation
IOUTFS set to 20 mA
PLL clock multiplier disabled
Note that the majority of the ac characterization curves for the
AD9772A are performed with these operating conditions.
DIGITAL INPUTS/OUTPUTS
The AD9772A consists of several digital input pins used for
data, clock, and control purposes. It also contains a single
digital output pin, PLLLOCK, which is used to monitor the
status of the internal PLL clock multiplier or provide a 1× clock
output. The 14-bit parallel data inputs follow standard positive
binary coding, where DB13 is the most significant bit (MSB)
and DB0 is the least significant bit (LSB). IOUTA produces a full-
scale output current when all data bits are at Logic 1. IOUTB
produces a complementary output with the full-scale current
split between the two outputs as a function of the input code.
The digital interface is implemented using an edge-triggered
master slave latch and is designed to support an input data rate as
high as 160 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width, as shown in Figure 2 and
Figure 3. The setup and hold times can also be varied within the
clock cycle as long as the specified minimum times are met. The
digital inputs (excluding CLK+ and CLK) are CMOS compatible
with its logic thresholds, VTHRESHOLD, set to approximately half the
digital positive supply (that is, DVDD or CLKVDD) or
VTHRESHOLD = DVDD/2 (±20%)
The internal digital circuitry of the AD9772A is capable of
operating over a digital supply range of 3.1 V to 3.5 V. As a
result, the digital inputs can also accommodate TTL levels when
DVDD is set to accommodate the maximum high level voltage
of the TTL drivers VOH(MAX). Although a DVDD of 3.3 V
typically ensures proper compatibility with most TTL logic
families, series 200 Ω resistors are recommended between the
TTL logic driver and digital inputs to limit the peak current
through the ESD protection diodes if VOH(MAX) exceeds DVDD
by more than 300 mV. Figure 42 shows the equivalent digital
input circuit for the data and control inputs.
DIGITAL
INPUT
DVDD
02
25
3-
0
42
Figure 42. Equivalent Digital Input
The AD9772A features a flexible differential clock input operating
from separate supplies (that is, CLKVDD, CLKCOM) to achieve
optimum jitter performance. The two clock inputs, CLK+ and
CLK, can be driven from a single-ended or differential clock
source. For single-ended operation, CLK+ should be driven by a
single-ended logic source, and CLK should be set to the logic
source’s threshold voltage via a resistor divider/capacitor network
referenced to CLKVDD as shown in Figure 43. For differential
operation, both CLK+ and CLK should be biased to CLKVDD/2
via a resistor divider network as shown in Figure 44. An RF
transformer as shown in Figure 7 can also be used to convert a
single-ended clock input to a differential clock input.
RSERIES
VTHRESHOLD
AD9772A
CLK+
CLKVDD
CLK–
CLKCOM
0.1F
1k
02
25
3-
04
3
B
Figure 43. Single-Ended Clock Interface
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9772A-EB | 制造商:Analog Devices 功能描述:14 BIT DAC W/2X INTERPOLATION 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9772A - Bulk |
| AD9772A-EBZ | 功能描述:BOARD EVAL FOR AD9772A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9772AST | 制造商:Rochester Electronics LLC 功能描述:14 BIT DAC W/2X INTERPOLA - Tape and Reel |
| AD9772EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter |
| AD9773 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Analog Devices: Data Converters: DAC 12-Bit, 10 ns to 100 ns Converters Selection Table |
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