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參數(shù)資料
| 型號(hào)： | AD9772AASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/40頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 160MSPS 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC+® |
| 設(shè)置時(shí)間： | 11ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 272mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 160M |
| 產(chǎn)品目錄頁面： | 785 (CN2011-ZH PDF) |
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AD9772A
Rev. C | Page 19 of 40
Zero-Stuffing Option Description
As shown in Figure 29, a zero or null in the frequency response
(after interpolation and DAC reconstruction) occurs at the final
DAC update rate (that is, 2× fDATA) due to the inherent sin(x)/x
roll-off response of the DAC. In baseband applications, this roll-
off in the frequency response may not be as problematic
because much of the desired signal energy remains below
fDATA/2 and the amplitude variation is not as severe. However, in
direct IF applications interested in extracting an image above
fDATA/2, this roll-off may be problematic due to the increased
pass-band amplitude variation as well as the reduced signal
level of the higher images.
FREQUENCY (
fDATA)
0
–10
–40
0
4.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
–20
–30
WITH
ZERO-STUFFING
WITHOUT
ZERO-STUFFING
BASEBAND
REGION
RO
L
-O
F
(
d
B
F
S
)
02
25
3-
02
9
Figure 29. Effects of Zero-Stuffing on the Sin(x)/x Response of the DAC
For instance, if the digital data into the AD9772A represents a
baseband signal centered around fDATA/4 with a pass band of
fDATA/10, the reconstructed baseband signal output from the
AD9772A experiences only a 0.18 dB amplitude variation over
its pass band, with the first image occurring at 7/4 × fDATA and
exhibiting 17 dB of attenuation relative to the fundamental.
However, if the high-pass filter response is selected, the AD9772A
produces pairs of images at [(2N + 1) × fDATA] ± fDATA/4, where
N = 0, 1, and so on. Note that due to the sin(x)/x response of the
DAC, only the lower or upper sideband images centered around
fDATA may be useful, although they are attenuated by 2.1 dB and
6.54 dB and have a pass-band amplitude roll-off of 0.6 dB and
1.3 dB, respectively.
To improve on the pass-band flatness of the desired image
and/or to extract higher images (that is, 3 × fDATA ± fFUNDAMENTAL),
the zero-stuffing option should be employed by bringing the
MOD1 pin high. This option increases the effective DAC
update rate by another factor of 2 because a midscale sample
(that is, 10 0000 0000 0000) is inserted after every data sample
originating from the 2× interpolation filter. A digital multiplexer
switching at a rate of 4 × fDATA between the interpolation filter
output and a data register containing the midscale data sample is
used as shown in Figure 28 to implement this option. Therefore,
the DAC output is now forced to return to its differential midscale
current value (that is, IOUTA IOUTB at 0 mA) after reconstructing
each data sample from the digital filter.
The net effect is to increase the DAC update rate such that the
zero in the sin(x)/x frequency response occurs at 4 × fDATA
accompanied by a corresponding reduction in output power as
shown in Figure 29. Note that if the high-pass response of the
2× interpolation filter is also selected, this action can be
modeled as a quarter-wave digital mixing process, because this
is equivalent to digitally mixing the impulse response of the
low-pass filter with a square wave having a frequency of exactly
fDATA (that is, fDAC/4).
It is important to realize that the zero-stuffing option by itself
does not change the location of the images, but rather changes
their signal level, amplitude flatness, and relative weighting. For
instance, in the previous example, the pass-band amplitude
flatness of the lower and upper sideband images centered
around fDATA are improved to 0.14 dB and 0.24 dB, respectively,
while the signal level changes to 6.5 dBFS and 7.5 dBFS. The
lower or upper sideband image centered around 3 × fDATA
exhibit an amplitude flatness of 0.77 dB and 1.29 dB with signal
levels of approximately 14.3 dBFS and 19.2 dBFS.
PLL CLOCK MULTIPLIER OPERATION
The phase-lock loop (PLL) clock multiplier circuitry, along with
the clock distribution circuitry, can produce the necessary
internally synchronized 1×, 2×, and 4× clocks for the edge-
triggered latches, 2× interpolation filter, zero-stuffing
multiplier, and DAC. Figure 30 shows a functional block
diagram of the PLL clock multiplier, which consists of a phase
detector, a charge pump, a voltage controlled oscillator (VCO),
a prescaler, and digital control input/output. The clock
distribution circuitry generates all the internal clocks for a given
mode of operation. The charge pump and VCO are powered
from PLLVDD, and the differential clock input buffer, phase
detector, prescaler, and clock distribution circuitry are powered
from CLKVDD. To ensure optimum phase noise performance
from the PLL clock multiplier and clock distribution circuitry,
PLLVDD and CLKVDD must originate from the same clean
analog supply.
CHARGE
PUMP
PHASE
DETECTOR
EXT/INT
CLOCK CONTROL
PRESCALER
CLKVDD
OUT1×
CLKCOM
MO
D
1
MO
D
0
RE
S
E
T
CLK+
LPF
PLLVDD
DNC
2.7V
TO
3.6V
PLLCOM
DI
V
1
DI
V
0
CLOCK
DISTRIBUTION
–
+
PLLLOCK
CLK–
VCO
AD9772A
02
25
3-
03
0
Figure 30. Clock Multiplier with PLL Clock Multiplier Enabled
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9772AASTZRL | 功能描述:IC DAC 14BIT 160MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9772A-EB | 制造商:Analog Devices 功能描述:14 BIT DAC W/2X INTERPOLATION 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9772A - Bulk |
| AD9772A-EBZ | 功能描述:BOARD EVAL FOR AD9772A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9772AST | 制造商:Rochester Electronics LLC 功能描述:14 BIT DAC W/2X INTERPOLA - Tape and Reel |
| AD9772EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter |
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