參數(shù)資料
型號： AD9644CCPZ-80
廠商： Analog Devices Inc
文件頁數(shù)： 30/44頁
文件大?。?/td> 0K
描述： IC ADC 14BIT 80MSPS 3V 48LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 460mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤
輸入數(shù)目和類型： 2 個差分，雙極
AD9644
Data Sheet
Rev. C | Page 36 of 44
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default/
Comments
0x24
BIST signature
LSB (local)
BIST signature[7:0]
0x00
Read only
0x25
BIST signature
MSB (local)
BIST signature[15:8]
0x00
Read only
0x3A
Sync control
(global)
Open
Clock
divider
next sync
only
Clock
divider
sync
enable
Master sync
buffer
enable
0x00
JESD204A Configuration Registers
0x5E
JESD204A
quick
configure
(global)
Open
000 = default—configuration
determined by other registers
001 = two converters using two links
with one lane per link
010 = two converters using one link with
two lanes per link
011 = two converters using one link and
a single lane
100 to 111: reserved
0x00
Changes
settings of
Address
0x5F to
Address
0x60 and
Address
0x6E to
Address
0x72
(self
clearing)
0x5F
JESD204A
lane
assignment
(global)
Open
JESD204A serial lane control
0000 = one lane per link. Link A: Lane 0 sent on Lane A,
Link B: Lane 0 Sent on Lane B
0001 = one lane per link. Link A: Lane 0 sent on Lane B,
Link B: Lane 0 Sent on Lane A.
0010 = two lanes per link. Link A: Lane 0, Lane 1 sent on
Lane A, Lane B. Link B disabled.
0011 = two lanes per link. Link A: Lane 0, Lane 1 sent on
Lane B, Lane A. Link B disabled.
0100 = two lanes per link. Link B: Lane 0, Lane 1 sent on
Lane A, Lane B. Link A disabled.
0101 = two lanes per link. Link B: Lane 0, 1 sent on
Lane B, Lane A. Link A disabled.
0110 to 1111: reserved
0x00
0x60
JESD204A
Link Control
Register 1
(local)
Open
Serial
tail bit
enable
Serial test
sample enable
Serial
lane
synchro
nization
enable
Serial lane alignment
sequence mode
00 = disabled
01 = enabled
10 = reserved
11 = always on test
mode
Frame
alignment
character
insertion
disable
Serial
transmit link
powered
down
0x00
0x61
JESD204A
Link Control
Register 2
(local)
Local DSYNC mode
00 = individual mode
01 = global mode
10 = DSYNC active
mode
11 = DSYNC pin
disabled
DSYNC pin
input inverted
CMOS
DSYNC
input
0 =
LVDS
1 =
CMOS
Open
Bypass
8b/10b
encoding
Invert
transmit
bits
Mirror serial
output bits
0x00
0x62
JESD204A
Link Control
Register 3
(local)
Disable
CHKSUM
Open
Link test generation input
selection
00 = 16-bit data injected at
sample input to the link
01 = 10-bit data injected at
output of 8b/10b encoder
10 = reserved
11 = reserved
Open
Link test generation mode
000 = normal operation
001 = alternating checker board
010 = 1/0 word toggle
011 = PN sequence—long
100 = PN sequence—short
101 = user test pattern data continuous
110 = user test pattern data single
111 = ramp output
0x00
0x63
JESD204A
Link Control
Register 4
(local)
Initial lane assignment sequence repeat count
0x00
0x64
JESD204A
device
identification
number (DID)
(local)
JESD204A serial device identification (DID) number
0x00
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參數(shù)描述
AD9644CCPZRL7-80 功能描述:IC ADC 14BIT 80MSPS 3V 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極
AD9645 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual, 14-Bit, 80 MSPS/125 MSPS, Serial LVDS
AD9645-125EBZ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 14Bit 125Msps Dual ADC w/serial LVDS RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
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AD9645BCPZ-80 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 14-Bit 80 MSPS Serial LVDS 1.8V RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體:
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