參數(shù)資料
型號(hào)： AD9644CCPZ-80
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 22/44頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT 80MSPS 3V 48LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 460mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： 2 個(gè)差分，雙極
Data Sheet
AD9644
Rev. C | Page 29 of 44
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9644 includes built-in test features designed to enable
verification of the integrity of each channel as well as facilitate
board level debugging. A BIST (built-in self-test) feature is included
that verifies the integrity of the digital datapath of the AD9644.
Various output test options are also provided to place predictable
values on the outputs of the AD9644.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9644 signal path. When enabled, the test runs from an internal
pseudorandom noise (PN) source through the digital datapath
starting at the ADC block output. The BIST sequence runs for
512 cycles and stops. The BIST signature value for Channel A
and/or Channel B is placed in Register 0x24 and Register 0x25.
The outputs are not disconnected during this test, so the PN
sequence can be observed as it runs. The PN sequence can be
continued from its last value or reset from the beginning, based
on the value programmed in Register 0x0E, Bit 2. The BIST
signature result varies based on the channel configuration.
OUTPUT TEST MODES
Digital Test patterns can be inserted at various points along the
signal path within the AD9644 as shown in Figure 70. The
ability to inject these signals at several locations facilitates
debugging of the JESD204A serial communication link.
The Register 0x0D allows test signals generated at the output of
the ADC core to be fed directly into the input of the serial Link.
The output test options available from Register 0x0D are shown
in Table 17. When an output test mode is enabled, the analog
section of the ADC is disconnected from the digital back end
blocks and the test pattern is run through the output formatting
block. Some of the test patterns are subject to output formatting,
and some are not. The seed value for the PN sequence tests can be
forced if the PN reset bits are used to hold the generator in reset
mode by setting Bit 4 or Bit 5 of Register 0x0D. These tests can
be performed with or without an analog signal (if present, the
analog signal is ignored), but they do require an encode clock.
For more information, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
There are nine digital output test pattern options available that
can be initiated through the SPI (see Table 14 for the output bit
sequencing options). This feature is useful when validating
receiver capture and timing. Some test patterns have two serial
sequential words and can be alternated in various ways, depending
on the test pattern selected. Note that some patterns do not
adhere to the data format select option. In addition, custom
user-defined test patterns can be assigned in the user pattern
registers (Address 0x19 through Address 0x20).
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 29 1 (511) bits. A description
of the PN sequence short and how it is generated can be found
in Section 5.1 of the ITU-T O.150 (05/96) recommendation.
The only difference is that the starting value must be a specific
value instead of all 1s (see Table 13 for the initial values).
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 223 1 (8,388,607) bits. A
description of the PN sequence long and how it is generated can
be found in Section 5.6 of the ITU-T O.150 (05/96) standard.
The only differences are that the starting value must be a specific
value instead of all 1s (see Table 13 for the initial values) and
that the AD9644 inverts the bit stream with relation to the ITU-T
standard.
Table 13. PN Sequence
Sequence
Initial
Value
First Three Output Samples
(MSB First)
PN Sequence Short
0x0092
0x125B, 0x3C9A, 0x2660
PN Sequence Long
0x3AFF
0x3FD7, 0x0002, 0x36E0
The Register 0x62 allows patterns similar to those described in
Table 14 to be input at different points along the data path. This
allows the user to provide predictable output data on the serial
link without it having been manipulated by the internal
formatting logic. Refer to Table 17 for additional information
on the test modes available in Register 0x62.
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