參數(shù)資料
型號: AD9644CCPZ-80
廠商: Analog Devices Inc
文件頁數(shù): 21/44頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 80MSPS 3V 48LFCSP
標準包裝: 1
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 串行,SPI?
轉換器數(shù)目: 2
功率耗散(最大): 460mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應商設備封裝: 48-LFCSP-VQ(7x7)
包裝: 托盤
輸入數(shù)目和類型: 2 個差分,雙極
AD9644
Data Sheet
Rev. C | Page 28 of 44
–600
–200
–400
0
200
400
600
610
620
0
635
–0.5
0.5
TIME (ps)
ULS
400
200
0
–200
–400
VO
L
T
A
G
E
(m
V)
HEIGHT1: EYE DIAGRAM
PERIOD1: HISTOGRAM
WIDTH@BER1: BATHTUB
1
20,000
25,000
15,000
10,000
5000
0
HI
T
S
615
625
630
100
10–2
10–4
10–6
10–8
10–10
10–12
10–14
BE
R
3
+
4
+
09
180
-09
4
EYE: TRANSITION BITS
OFFSET: –0.004
ULS: 8000; 639999, TOTAL: 8000; 639999
0.781
Figure 68. AD9644-80 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations
–300
–100
–200
0
100
200
300
305
315
0
330 335
–0.5
0.5
TIME (ps)
ULS
500
400
300
200
100
0
–100
–300
–400
–500
–200
VO
L
T
A
G
E
(m
V)
HEIGHT1: EYE DIAGRAM
PERIOD1: HISTOGRAM
WIDTH@BER1: BATHTUB
1
45,000
50,000
40,000
35,000
20,000
25,000
30,000
15,000
10,000
5000
0
HI
T
S
310
320 325
100
10–2
10–4
10–6
10–8
10–10
10–12
10–14
BE
R
3
4
09
180
-06
9
0.742
EYE: TRANSITION BITS
OFFSET: –0.004
ULS: 8000; 124,0001, TOTAL: 8000; 124,0001
Figure 69. AD9644-155 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations
Figure 68 and Figure 69 shows an example of the digital output
(default) data eye and a time interval error (TIE) jitter histogram.
Additional SPI options allow the user to further increase the
output driver voltage swing of all four outputs to drive longer
trace lengths (see Address 0x15 in Table 17). Even though this
produces sharper rise and fall times on the data edges and is less
prone to bit errors, the power dissipation of the DRVDD supply
increases when this option is used. See the Memory Map section
for more details.
The format of the output data is twos complement by default.
Table 12 provides an example of this output coding format.
To change the output data format to offset binary or gray code,
see the Memory Map section (Address 0x14 in Table 17).
Table 12. Digital Output Coding
Code
(VIN+ ) (VIN ),
Input Span = 1.75 V p-p (V)
Digital Output
Twos Complement
([D13:D0])
8191
+0.875
01 1111 1111 1111
0
0.00
00 0000 0000 0000
1
0.000107
11 1111 1111 1111
8192
0.875
10 0000 0000 0000
The lowest typical clock rate is 40 MSPS. For clock rates slower
than 60 MSPS, the user should set Bit 3 to 0 in the serial control
register (Address 0x21 in Table 17). This option sets the PLL
loop bandwidth to use clock rates between 40 MSPS and
60 MSPS.
Setting Bit 2 in the output mode register (Address 0x14) allows
the user to invert the digital samples from their nominal state.
As shown in Figure 64, the MSB is transmitted first in the data
output serial stream.
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