Data Sheet
AD9515
Rev. A | Page 3 of 28
SPECIFICATIONS
Typical (typ) is given for VS = 3.3 V ± 5%, TA = 25°C, RSET = 4.12 k, LVPECL swing = 790 mV, unless otherwise noted. Minimum (min)
and maximum (max) values are given over full VS and TA (40°C to +85°C) variation.
CLOCK INPUT
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CLOCK INPUT (CLK)
0
1.6
GHz
150
mV p-p
Input Common-Mode Voltage, V
CM
1.5
1.6
1.7
V
Self-biased; enables ac coupling
Input Common-Mode Range, V
CMR
1.3
1.8
V
With 200 mV p-p signal applied; dc-coupled
Input Sensitivity, Single-Ended
150
mV p-p
CLK ac-coupled; CLKB ac-bypassed to RF ground
Input Resistance
4.0
4.8
5.6
k
Self-biased
Input Capacitance
2
pF
1A slew rate of 1 V/ns is required to meet jitter, phase noise, and propagation delay specifications.
CLOCK OUTPUTS
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL CLOCK OUTPUT
Termination = 50 to V
S 2 V
(OUT0) Differential
Output Frequency
0
1.6
GHz
Output High Voltage (V
OH)
V
S 1.1
V
S 0.96
V
S 0.82
V
Output Low Voltage (V
OL)
V
S 1.90
V
S 1.76
V
S 1.52
V
Output Differential Voltage (V
OD)
640
790
960
mV
LVDS CLOCK OUTPUT
Termination = 100 differential
(OUT1) Differential
Output Frequency
0
800
MHz
Differential Output Voltage (V
OD)
250
350
450
mV
Delta V
OD
30
mV
Output Offset Voltage (V
OS)
1.125
1.23
1.375
V
Delta V
OS
25
mV
Short-Circuit Current (I
SA, ISB)
14
24
mA
Output shorted to GND
CMOS CLOCK OUTPUT
Single-ended measurements; termination open
(OUT1) Single-Ended
Complementary output on (OUT1B)
Output Frequency
0
250
MHz
With 5 pF load
Output Voltage High (V
OH)
V
S 0.1
V
@ 1 mA load
Output Voltage Low (V
OL)
0.1
V
@ 1 mA load