參數(shù)資料
型號: AD9515BCPZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 16/28頁
文件大?。?/td> 0K
描述: IC CLOCK DIST 2OUT PLL 32LFCSP
設計資源: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
標準包裝: 1,500
類型: 扇出緩沖器(分配),除法器
PLL:
輸入: 時鐘
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.6GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應商設備封裝: 32-LFCSP-VQ(5x5)
包裝: 帶卷 (TR)
配用: AD9515/PCBZ-ND - BOARD EVAL CLOCK 2CH AD9515
Data Sheet
AD9515
Rev. A | Page 23 of 28
When the delay block is OFF (bypassed), it is also powered
down.
OUTPUTS
The AD9515 offers three different output level choices:
LVPECL, LVDS, and CMOS. OUT0/OUT0B offers an LVPECL
differential output. The LVPECL differential voltage swing
(VOD) can be selected as either 400 mV or 790 mV (see Table 11).
OUT1/OUT1B can be selected as either an LVDS differential
output or a pair of CMOS single-ended outputs. If selected as
CMOS, OUT1 is a noninverted, single-ended output, and
OUT1B is an inverted, single-ended output.
GND
3.3V
OUTB
OUT
05597-026
Figure 31. LVPECL Output Simplified Equivalent Circuit
OUTB
OUT
3.5mA
05597-027
Figure 32. LVDS Output Simplified Equivalent Circuit
05597-028
OUT1/
OUT1B
VS
Figure 33. CMOS Equivalent Output Circuit
POWER SUPPLY
The AD9515 requires a 3.3 V ± 5% power supply for VS. The
tables in the Specifications section give the performance
expected from the AD9515 with the power supply voltage
within this range. In no case should the absolute maximum
range of 0.3 V to +3.6 V, with respect to GND, be exceeded
on Pin VS.
Good engineering practice should be followed in the layout of
power supply traces and the ground plane of the PCB. The
power supply should be bypassed on the PCB with adequate
capacitance (>10 F). The AD9515 should be bypassed with
adequate capacitors (0.1 F) at all power pins as close as
possible to the part. The layout of the AD9515 evaluation
board (AD9515/PCB) is a good example.
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