參數(shù)資料
型號: AD9515BCPZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 2/28頁
文件大小: 0K
描述: IC CLOCK DIST 2OUT PLL 32LFCSP
設(shè)計資源: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
標準包裝: 1,500
類型: 扇出緩沖器(分配),除法器
PLL:
輸入: 時鐘
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.6GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 帶卷 (TR)
配用: AD9515/PCBZ-ND - BOARD EVAL CLOCK 2CH AD9515
AD9515
Data Sheet
Rev. A | Page 10 of 28
POWER
Table 7.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER-ON SYNCHRONIZATION1
35
ms
See the Power-On SYNC section.
V
S Transit Time from 2.2 V to 3.1 V
POWER DISSIPATION
215
285
380
mW
Both outputs on. LVPECL (divide = 2), LVDS (divide = 2). No clock.
Does not include power dissipated in external resistors.
300
370
465
mW
Both outputs on. LVPECL (divide = 2), CMOS (divide = 2);
at 62.5 MHz out (5 pF load).
330
405
510
mW
Both outputs on. LVPECL, CMOS (divide = 2);
at 125 MHz out (5 pF load).
POWER DELTA
Divider (Divide = 2 to Divide = 1)
15
30
45
mW
For each divider. No clock.
LVPECL Output
65
90
125
mW
For each output. No clock.
LVDS Output
20
50
85
mW
No clock.
CMOS Output (Static)
30
40
50
mW
No clock.
CMOS Output (@ 62.5 MHz)
80
110
140
mW
Single-ended. At 62.5 MHz out with 5 pF load.
CMOS Output (@ 125 MHz)
110
150
190
mW
Single-ended. At 125 MHz out with 5 pF load.
Delay Block
30
45
65
mW
Off to 1.5 ns fs, delay word = 60; output clocking at 62.5 MHz.
1 This is the rise time of the V
S supply that is required to ensure that a synchronization of the outputs occurs on power-up. The critical factor is the time it takes the VS to
transition the range from 2.2 V to 3 .1 V. If the rise time is too slow, the outputs will not be synchronized.
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