AVDD = 1.8 V, DRVDD = 1.8 V, TMIN
參數(shù)資料
型號: AD9484BCPZRL7-500
廠商: Analog Devices Inc
文件頁數(shù): 21/24頁
文件大小: 0K
描述: IC ADC 8BIT 500MSPS 56LFCSP
標(biāo)準(zhǔn)包裝: 750
位數(shù): 8
采樣率(每秒): 500M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 720mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 56-LFCSP-VQ(8x8)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,雙極
AD9484
Rev. A | Page 6 of 24
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = 40°C, TMAX = +85°C, fIN = 1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 4.
Parameter
Temp
Min
Typ
Max
Unit
Maximum Conversion Rate
Full
500
MSPS
Minimum Conversion Rate
Full
50
MSPS
CLK+ Pulse Width High (tCH)1
Full
0.9
11
ns
CLK+ Pulse Width Low (tCL)1
Full
0.9
11
ns
Output (LVDS—SDR)1
Data Propagation Delay (tPD)
Full
0.85
ns
Rise Time (tR) (20% to 80%)
25°C
0.15
ns
Fall Time (tF) (20% to 80%)
25°C
0.15
ns
DCO Propagation Delay (tCPD)
Full
0.6
ns
Data to DCO Skew (tSKEW)
Full
0.07
+0.07
ns
Latency
Full
15
Clock cycles
Aperture Time (tA)
25°C
0.85
ns
Aperture Uncertainty (Jitter, tJ)
25°C
80
fs rms
1 See
.
Timing Diagram
N – 1
N
N + 2
N + 3
N + 4
N + 5
N + 1
CLK+
N – 15
N – 14
N – 13
N – 12
N – 11
CLK–
DCO+
DCO–
Dx+
Dx–
VIN+, VIN–
tA
tCH
tCL
1/
fS
tCPD
tSKEW
tPD
09
615-
002
Figure 2. Timing Diagram
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