參數(shù)資料
型號: AD9513BCPZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 1/28頁
文件大小: 0K
描述: IC CLOCK DIST 3OUT PLL 32LFCSP
標(biāo)準(zhǔn)包裝: 1,500
類型: 扇出緩沖器(分配),除法器
PLL:
輸入: 時(shí)鐘
輸出: CMOS,LVDS
電路數(shù): 1
比率 - 輸入:輸出: 1:3
差分 - 輸入:輸出: 是/是
頻率 - 最大: 800MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 帶卷 (TR)
配用: AD9513/PCBZ-ND - BOARD EVAL FOR AD9513
800 MHz Clock Distribution IC, Dividers,
Delay Adjust, Three Outputs
AD9513
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
FEATURES
1.6 GHz differential clock input
3 programmable dividers
Divide-by in range from1 to 32
Phase select for coarse delay adjust
Three 800 MHz/250 MHz LVDS/CMOS clock outputs
Additive output jitter 300 fs rms
Time delays up to 11.6 ns
Device configured with 4-level logic pins
Space-saving, 32-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
ATE
FUNCTIONAL BLOCK DIAGRAM
0
5595-
001
CLK
CLKB
SYNCB
RSET
VSGND
AD9513
VREF
S10 S9S8S7S6S5S4S3S2S1
S0
SETUP LOGIC
OUT0
OUT0B
/1. . . /32
LVDS/CMOS
OUT1
OUT1B
/1. . . /32
LVDS/CMOS
OUT2
OUT2B
/1. . . /32
LVDS/CMOS
t
Figure 1.
GENERAL DESCRIPTION
The AD9513 features a three-output clock distribution IC in a
design that emphasizes low jitter and phase noise to maximize
data converter performance. Other applications with
demanding phase noise and jitter requirements also benefit
from this part.
There are three independent clock outputs that can be set to
either LVDS or CMOS levels. These outputs operate to
800 MHz in LVDS mode and to 250 MHz in CMOS mode.
Each output has a programmable divider that can be set to
divide by a selected set of integers ranging from 1 to 32. The
phase of one clock output relative to the other clock output can
be set by means of a divider phase select function that serves as
a coarse timing adjustment.
One of the outputs features a delay element with three selectable
full-scale delay values (1.8 ns, 6.0 ns, and 11.6 ns), each with
16 steps of fine adjustment.
The AD9513 does not require an external controller for
operation or setup. The device is programmed by means of
11 pins (S0 to S10) using 4-level logic. The programming pins
are internally biased to VS. The VREF pin provides a level of
VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.
The AD9513 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9513 is available in a 32-lead LFCSP and operates from
a single 3.3 V supply. The temperature range is 40°C to +85°C.
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