參數(shù)資料
型號(hào): AD9513BCPZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 28/28頁
文件大小: 0K
描述: IC CLOCK DIST 3OUT PLL 32LFCSP
標(biāo)準(zhǔn)包裝: 1,500
類型: 扇出緩沖器(分配),除法器
PLL:
輸入: 時(shí)鐘
輸出: CMOS,LVDS
電路數(shù): 1
比率 - 輸入:輸出: 1:3
差分 - 輸入:輸出: 是/是
頻率 - 最大: 800MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 帶卷 (TR)
配用: AD9513/PCBZ-ND - BOARD EVAL FOR AD9513
AD9513
Rev. 0 | Page 9 of 28
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DELAY BLOCK ADDITIVE TIME JITTER1
100 MHz output; incremental additive jitter1
Delay FS = 1.8 ns Fine Adj. 00000
0.71
ps rms
Delay FS = 1.8 ns Fine Adj. 11111
1.2
ps rms
Delay FS = 6.0 ns Fine Adj. 00000
1.3
ps rms
Delay FS = 6.0 ns Fine Adj. 11111
2.7
ps rms
Delay FS = 11.6 ns Fine Adj. 00000
2.0
ps rms
Delay FS = 11.6 ns Fine Adj. 11111
2.8
ps rms
1 This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
SYNCB, VREF, AND SETUP PINS
Table 6.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SYNCB
Logic High
2.7
V
Logic Low
0.40
V
Capacitance
2
pF
VREF
Output Voltage
0.62VS
0.76VS
V
Minimum maximum from 0 mA to 1 mA load
S0 TO S10
Levels
0
0.1VS
V
1/3
0.2VS
0.45VS
V
2/3
0.55VS
0.8VS
V
1
0.9VS
V
POWER
Table 7.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER-ON SYNCHRONIZATION1
35
ms
See the Power-On SYNC section.
VS Transit Time from 2.2 V to 3.1 V
POWER DISSIPATION
175
325
575
mW
All three outputs on. LVDS (divide = 2). No clock. Does not include
power dissipated in external resistors.
240
460
615
mW
All three outputs on. CMOS (divide = 2); 62.5 MHz out (5 pF load).
320
605
840
mW
All three outputs on. CMOS (divide = 2); 125 MHz out (5 pF load).
POWER DELTA
Divider (Divide = 2 to Divide = 1)
15
30
45
mW
For each divider. No clock.
LVDS Output
20
50
85
mW
No clock.
CMOS Output (Static)
30
40
50
mW
No clock.
CMOS Output (@ 62.5 MHz)
65
110
155
mW
Single-ended. At 62.5 MHz out with 5 pF load.
CMOS Output (@ 125 MHz)
70
145
220
mW
Single-ended. At 125 MHz out with 5 pF load.
Delay Block
30
45
65
mW
Off to 1.8 ns fs, delay word = 60; output clocking at 62.5 MHz.
1 This is the rise time of the VS supply that is required to ensure that a synchronization of the outputs occurs on power-up. The critical factor is the time it takes the VS to
transition the range from 2.2 V to 3 .1 V. If the rise time is too slow, the outputs are not synchronized.
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