參數(shù)資料
型號: AD9273BSVZ-50
廠商: Analog Devices Inc
文件頁數(shù): 37/48頁
文件大小: 0K
描述: IC ADC ASD OCTAL 50MSPS 100-TQFP
標準包裝: 1
類型: AAF,ADC,交叉點開關(guān),LNA,VGA
分辨率(位): 12 b
采樣率(每秒): 50M
數(shù)據(jù)接口: 串行,SPI?
電壓電源: 模擬和數(shù)字
電源電壓: 1.8V,3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應商設備封裝: 100-TQFP-EP(14x14)
包裝: 托盤
產(chǎn)品目錄頁面: 780 (CN2011-ZH PDF)
AD9273
Rev. B | Page 42 of 48
Addr.
(Hex)
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
Default Notes/
Comments
0F
FLEX_CHANNEL_
INPUT
Filter cutoff frequency control
0000 = 1.3 × 1/3 × fSAMPLE
0001 = 1.2 × 1/3 × fSAMPLE
0010 = 1.1 × 1/3 × fSAMPLE
0011 = 1.0 × 1/3 × fSAMPLE (default)
0100 = 0.9 × 1/3 × fSAMPLE
0101 = 0.8 × 1/3 × fSAMPLE
0110 = 0.7 × 1/3 × fSAMPLE
1000 = 1.3 × 1/4.5 × fSAMPLE
1001 = 1.2 × 1/4.5 × fSAMPLE
1010 = 1.1 × 1/4.5 × fSAMPLE
1011 = 1.0 × 1/4.5 × fSAMPLE
1100 = 0.9 × 1/4.5 × fSAMPLE
1101 = 0.8 × 1/4.5 × fSAMPLE
1110 = 0.7 × 1/4.5 × fSAMPLE
X
0x30
Antialiasing filter
cutoff (global).
10
FLEX_OFFSET
X
6-bit LNA offset adjustment
10 0000 = LNA bias high, mid-high, mid-low (default)
10 0001 = LNA bias low
0x20
LNA force offset
correction
(local).
11
FLEX_GAIN
X
PGA gain
00 = 21 dB
01 = 24 dB (default)
10 = 27 dB
11 = 30 dB
LNA gain
00 = 15.6 dB
01 = 17.9 dB
10 = 21.3 dB
(default)
0x06
LNA and PGA
gain adjustment
(global).
12
BIAS_CURRENT
X
1
X
LNA bias
00 = high
01 = mid-high
(default)
10 = mid-low
11 = low
0x08
LNA bias current
adjustment
(global).
14
OUTPUT_MODE
X
0 = LVDS
ANSI-644
(default)
1 = LVDS
low power,
(IEEE
1596.3
similar)
X
Output
invert
1 = on
0 = off
(default)
00 = offset binary
(default)
01 = twos
complement
0x00
Configures the
outputs and the
format of the data
(Bits[7:3] and
Bits[1:0] are global;
Bit 2 is local).
15
OUTPUT_ADJUST
X
Output driver
termination
00 = none (default)
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
X
DCO±
and
FCO±
2× drive
strength
1 = on
0 = off
(default)
0x00
Determines LVDS
or other output
properties. Pri-
marily functions to
set the LVDS span
and common-
mode levels in
place of an
external resistor
(Bits[7:1] are global;
Bit 0 is local).
16
OUTPUT_PHASE
X
0011 = output clock phase adjust
(0000 through 1010)
0000 = 0° relative to data edge
0001 = 60° relative to data edge
0010 = 120° relative to data edge
0011 = 180° relative to data edge (default)
0100 = 240° relative to data edge
0101 = 300° relative to data edge
0110 = 360° relative to data edge
0111 = 420° relative to data edge
1000 = 480° relative to data edge
1001 = 540° relative to data edge
1010 = 600° relative to data edge
1011 to 1111 = 660° relative to data edge
0x03
On devices that
utilize global
clock divide,
determines which
phase of the
divider output is
used to supply
the output clock.
Internal latching
is unaffected.
18
FLEX_VREF
X
0 =
internal
reference
1 =
external
reference
X
0x00
Select internal
reference
(recommended
default) or external
reference (global).
相關(guān)PDF資料
PDF描述
AD9272BSVZ-40 IC ADC OCT 12BIT 40MSPS 100-TQFP
VE-B4J-MY-S CONVERTER MOD DC/DC 36V 50W
MAX199BCNI+ IC DAS 12BIT 8CH 28-DIP
VE-B44-MY-S CONVERTER MOD DC/DC 48V 50W
MS3124P22-55S CONN RCPT 55POS JAM NUT W/SCKT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9273BSVZRL-25 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12Bit 25 MSPS Octal ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體:
AD9273BSVZRL-40 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12Bit 40 MSPS Octal ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體:
AD9273BSVZRL-50 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12Bit 50 MSPS Octal ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體:
AD9273XBCZ 功能描述:IC ADC 制造商:analog devices inc. 系列:* 零件狀態(tài):上次購買時間 標準包裝:1
AD9276 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal LNA/VGA/AAF/12-Bit ADC and CW I/Q Demodulator