參數(shù)資料
型號: AD9230BCPZ-170
廠商: Analog Devices Inc
文件頁數(shù): 31/32頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 170MSPS 56-LFCSP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
采樣率(每秒): 170M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 371mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 56-LFCSP-VQ(8x8)
包裝: 托盤
輸入數(shù)目和類型: 1 個差分,單極
AD9230
Rev. 0 | Page 8 of 32
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Rating
ELECTRICAL
AVDD to AGND
0.3 V to +2.0 V
DRVDD to DRGND
0.3 V to +2.0 V
AGND to DRGND
0.3 V to +0.3 V
AVDD to DRVDD
2.0 V to +2.0 V
D0+/D0 through D13+/D13
to DRGND
0.3 V to DRVDD + 0.3 V
DCO to DRGND
0.3 V to DRVDD + 0.3 V
OR to DGND
0.3 V to DRVDD + 0.3 V
CLK+ to AGND
0.3 V to +3.9 V
CLK to AGND
0.3 V to +3.9 V
VIN+ to AGND
0.3 V to AVDD + 0.2 V
VIN to AGND
0.3 V to AVDD + 0.2 V
SDIO/DCS to DGND
0.3 V to DRVDD + 0.3 V
PDWN to AGND
0.3 V to +3.9 V
CSB to AGND
0.3 V to +3.9 V
SCLK/DFS to AGND
0.3 V to +3.9 V
ENVIRONMENTAL
Storage Temperature Range
65°C to +125°C
Operating Temperature Range
40°C to +85°C
Lead Temperature
(Soldering 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the
customer board increases the reliability of the solder joints,
maximizing the thermal capability of the package.
Table 6.
Package Type
θJA
θJC
Unit
56-Lead LFCSP (CP-48-3)
30.4
2.9
°C/W
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, metal in direct contact with the package leads from
metal traces, and through holes, ground, and power planes
reduces the θJA.
ESD CAUTION
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