參數(shù)資料
型號： AD9230BCPZ-170
廠商： Analog Devices Inc
文件頁數(shù)： 14/32頁
文件大小： 0K
描述： IC ADC 12BIT 170MSPS 56-LFCSP
標準包裝： 1
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 串行，SPI?
轉換器數(shù)目： 1
功率耗散（最大）： 371mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
供應商設備封裝： 56-LFCSP-VQ（8x8）
包裝： 托盤
輸入數(shù)目和類型： 1 個差分，單極
AD9230
Rev. 0 | Page 21 of 32
THEORY OF OPERATION
The AD9230 architecture consists of a front-end sample and
hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 12-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample, while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended mode. The output-
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
ANALOG INPUT AND VOLTAGE REFERENCE
The analog input to the AD9230 is a differential buffer. For best
dynamic performance, the source impedances driving VIN+
and VIN should be matched such that common-mode settling
errors are symmetrical. The analog input is optimized to
provide superior wideband performance and requires that the
analog inputs be driven differentially. SNR and SINAD
performance degrades significantly if the analog input is driven
with a single-ended signal.
A wideband transformer, such as Mini-Circuits ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip resistor divider to a
nominal 1.3 V.
An internal differential voltage reference creates positive and
negative reference voltages that define the 1.25 V p-p fixed span
of the ADC core. This internal voltage reference can be adjusted
by means of SPI control. See the AD9230 Configuration Using
the SPI section for more details.
Differential Input Configurations
Optimum performance is achieved while driving the AD9230
in a differential input configuration. For baseband applications,
the AD8138 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
VIN+
VIN–
AVDD
CML
AD8138
523
499
33
49.9
1V p-p
0.1F
20pF
AD9230
0
6
002
-055
Figure 52. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers may not be adequate to achieve
the true performance of the AD9230. This is especially true in
IF undersampling applications where frequencies in the 70 MHz
to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration. The signal characteristics must be considered
when selecting a transformer. Most RF transformers saturate at
frequencies below a few MHz, and excessive signal power can
also cause core saturation, which leads to distortion.
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
or removed.
VIN+
VIN–
15
50
1.25V p-p
0.1F
2pF
AD9230
060
02
-056
Figure 53. Differential Transformer—Coupled Configuration
As an alternative to using a transformer-coupled input at
frequencies in the second Nyquist zone, the AD8352 differential
driver can be used (see Figure 54).
06002-
059
AD9230
AD8352
0
R
0
CD
RD
RG
0.1F
VIN+
VIN– CML
C
0.1F
16
1
2
3
4
5
11
R
0.1F
10
8, 13
14
VCC
200
ANALOG INPUT
Figure 54. Differential Input Configuration Using the AD8352
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相關代理商/技術參數(shù)
參數(shù)描述
AD9230BCPZ-210 功能描述:模數(shù)轉換器 - ADC IC 12B 210Msps 1.8V RoHS:否 制造商:Analog Devices 通道數(shù)量: 結構: 轉換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體:
AD9230BCPZ-250 制造商:Analog Devices 功能描述:ADC Single Pipelined 250Msps 12-bit Parallel/LVDS 56-Pin LFCSP EP Tray 制造商:Analog Devices 功能描述:ADC SGL PIPELINED 250MSPS 12-BIT PARALLEL 56LFCSP EP - Trays 制造商:Analog Devices 功能描述:IC ADC 12BIT 250MSPS LFCSP-56 制造商:Analog Devices Inc. 功能描述:Analog to Digital Converters - ADC 12-Bit 250 Msps ADC 制造商:Analog Devices 功能描述:IC, ADC, 12BIT, 250MSPS, LFCSP-56; Resolution (Bits):12bit; Sampling Rate:250MSPS; Supply Voltage Type:Single; Supply Voltage Min:1.7V; Supply Voltage Max:1.9V; Supply Current:181mA; Digital IC Case Style:CSP; No. of Pins:56 ;RoHS Compliant: Yes 制造商:Analog Devices 功能描述:CONVERTER - ADC
AD9230BCPZRL7-170 功能描述:模數(shù)轉換器 - ADC IC 12B 170Msps 1.8V RoHS:否 制造商:Analog Devices 通道數(shù)量: 結構: 轉換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體:
AD9230XCPZ-170 制造商:Analog Devices 功能描述:12-BIT, 170/210/250 MSPS 1.8 V A/D CONVERTER - Trays
AD9230XCPZ-210 制造商:Analog Devices 功能描述:12-BIT, 170/210/250 MSPS 1.8 V A/D CONVERTER - Trays
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