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AD9230
Rev. 0 | Page 5 of 32
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = 40°C, TMAX = +85°C, fIN = 1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 3.
AD9230-170
AD9230-210
AD9230-250
Temp
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
CLOCK INPUTS
Logic Compliance
Full
CMOS/LVDS/LVPECL
Internal Common-Mode Bias
Full
1.2
V
Differential Input Voltage
Full
0.2
6
0.2
6
0.2
6
V p-p
Input Voltage Range
Full
AVDD
0.3
AVDD +
1.6
AVDD
0.3
AVDD +
1.6
AVDD
0.3
AVDD +
1.6
V
Input Common-Mode Range
Full
1.1
AVDD
1.1
AVDD
1.1
AVDD
V
High Level Input Voltage (VIH)
Full
1.2
3.6
1.2
3.6
1.2
3.6
V
Low Level Input Voltage (VIL)
Full
0
0.8
0
0.8
0
0.8
V
High Level Input Current (IIH)
Full
10
+10
10
+10
10
+10
μA
Low Level Input Current (IIL)
Full
10
+10
10
+10
10
+10
μA
Input Resistance
(Differential)
Full
16
20
24
16
20
24
16
20
24
kΩ
Input Capacitance
Full
4
pF
LOGIC INPUTS
Logic 1 Voltage
Full
0.8 ×
VDD
0.8 ×
VDD
0.8 ×
VDD
V
Logic 0 Voltage
Full
0.2 ×
AVDD
0.2 ×
AVDD
0.2 ×
AVDD
V
Logic 1 Input Current (SDIO)
Full
0
μA
Logic 0 Input Current (SDIO)
Full
60
μA
Logic 1 Input Current
(SCLK, PDWN, CSB, RESET)
Full
55
50
μA
Logic 0 Input Current
(SCLK, PDWN, CSB, RESET)
Full
0
μA
Input Capacitance
25°C
4
pF
VOD Differential Output Voltage
Full
247
454
247
454
247
454
mV
VOS Output Offset Voltage
Full
1.125
1.375
1.125
1.375
1.125
1.375
V
Output Coding
Twos complement, Gray code, or offset binary (default)
1 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed. 2 LVDS RTERMINATION = 100 Ω.