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參數(shù)資料
| 型號： | AD807 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming(帶數(shù)字轉(zhuǎn)換,時鐘恢復(fù)和重定時功能的光纖接收器) |
| 中文描述： | 光纖接收器與量化和時鐘恢復(fù)和數(shù)據(jù)重定時（帶數(shù)字轉(zhuǎn)換，時鐘恢復(fù)和重定時功能的光纖接收器） |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 234K |
| 代理商： | AD807 |
REV. A
–8–
AD807
A lower damping ratio allows a faster frequency acquisition;
generally the acquisition time scales directly with the capacitor
value. However, at damping ratios approaching one, the acquisi-
tion time no longer scales directly with capacitor value. T he
acquisition time has two components: frequency acquisition and
phase acquisition. T he frequency acquisition always scales with
capacitance, but the phase acquisition is set by the loop band-
width of the PL L and is independent of the damping ratio.
T hus, the 0.06% fractional loop bandwidth sets a minimum
acquisition time of 2000 bit periods. Note the acquisition time
for a damping factor of one is 15,000 bit periods. T his com-
prises 13,000 bit periods for frequency acquisition and 2,000 bit
periods for phase acquisition. Compare this to the 400,000 bit
periods acquisition time specified for a damping ratio of 5; this
consists entirely of frequency acquisition, and the 2,000 bit
periods of phase acquisition is negligible.
While a lower damping ratio affords faster acquisition, it also al-
lows more peaking in the jitter transfer response (jitter peaking).
For example, with a damping ratio of 10, the jitter peaking is
0.02 dB, but with a damping ratio of 1, the peaking is 2 dB.
Center Frequency Clamp (Figure 19)
An N-channel FET circuit can be used to bring the AD807
VCO center frequency to within
±
10% of 155 MHz when
SDOUT indicates a Loss of Signal (LOS). T his effectively re-
duces the frequency acquisition time by reducing the frequency
error between the VCO frequency and the input data frequency
at clamp release. T he N-FET can have “on” resistance as high
as 1 k
and still attain effective clamping. However, the chosen
N-FET should have greater than 10 M
“off” resistance and
less than 100 nA leakage current (source and drain) so as not to
alter normal PLL performance.
1
2
5
6
7
3
4
8
16
15
12
11
10
14
13
9
V
EE
SDOUT
AV
CC2
PIN
NIN
AV
CC1
THRADJ
AV
EE
DATAOUTN
DATAOUTP
CLKOUTN
CLKOUTP
V
CC1
CF1
CF2
V
CC2
AD807
N_FET
C
D
Figure 19. Center Frequency Clamp Schematic
10
20k
10k
100
1k
C
D
PEAK
0.1 0.12
0.15 0.08
0.22 0.06
0.33 0.04
0
FREQUENCY IN kHz
Figure 20. J itter Transfer vs. C
D
POSITIVE
PEAK
DETECTOR
NEGATIVE
PEAK
DETECTOR
LEVEL
SHIFT
DOWN
LEVEL
SHIFT
UP
∑
THRESHOLD
BIAS
+
PIN
NIN
SDOUT
IHYS
+
AD807
COMPARATOR STAGES
& CLOCK RECOVERY PLL
ITHR
Figure 17. Signal Level Detect Circuit Block Diagram
Phase-Locked Loop
T he phase-locked loop recovers clock and retimes data from
NRZ data. T he architecture uses a frequency detector to aid ini-
tial frequency acquisition; refer to Figure 18 for a block dia-
gram. Note the frequency detector is always in the circuit. When
the PLL is locked, the frequency error is zero and the frequency
detector has no further effect. Since the frequency detector is al-
ways in the circuit, no control functions are needed to initiate
acquisition or change mode after acquisition.
VCO
RETIMING
DEVICE
Φ
DET
∑
F
DET
DATA
INPUT
1
S
S + 1
RECOVERED CLOCK
RETIMED DATA
Figure 18. PLL Block Diagram
T he frequency detector delivers pulses of current to the charge
pump to either raise or lower the frequency of the VCO. During
the frequency acquisition process the frequency detector output
is a series of pulses of width equal to the period of the VCO.
T hese pulses occur on the cycle slips between the data fre-
quency and the VCO frequency. With a maximum density data
pattern (1010 . . . ), every cycle slip will produce a pulse at the
frequency detector output. However, with random data, not
every cycle slip produces a pulse. T he density of pulses at the
frequency detector output increases with the density of data
transitions. T he probability that a cycle slip will produce a pulse
increases as the frequency error approaches zero. After the fre-
quency error has been reduced to zero, the frequency detector
output will have no further pulses. At this point the PLL begins
the process of phase acquisition, with a settling time of roughly
2000 bit periods.
Jitter caused by variations of density of data transitions (pattern
jitter) is virtually eliminated by use of a new phase detector (pat-
ented). Briefly, the measurement of zero phase error does not
cause the VCO phase to increase to above the average run rate
set by the data frequency. T he jitter created by a 2
7
–1 pseudo-
random code is 1/2 degree, and this is small compared to ran-
dom jitter.
T he jitter bandwidth for the PLL is 0.06% of the center fre-
quency. T his figure is chosen so that sinusoidal input jitter at
92 kHz will be attenuated by 3 dB.
T he damping ratio of the PLL is user programmable with a
single external capacitor. At 155 MHz, a damping ratio of 5 is
obtained with a 0.15
μ
F capacitor. More generally, the damping
ratio scales as (f
DAT A
×
C
D
)
1/2
.
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