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參數(shù)資料
| 型號(hào)： | AD807 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming(帶數(shù)字轉(zhuǎn)換,時(shí)鐘恢復(fù)和重定時(shí)功能的光纖接收器) |
| 中文描述： | 光纖接收器與量化和時(shí)鐘恢復(fù)和數(shù)據(jù)重定時(shí)（帶數(shù)字轉(zhuǎn)換，時(shí)鐘恢復(fù)和重定時(shí)功能的光纖接收器） |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 234K |
| 代理商： | AD807 |
AD807
REV. A
–5–
Damping Factor,
ζ
Damping factor,
ζ
describes the compensation of the second or-
der PLL. A larger value of
ζ
corresponds to more damping and
less peaking in the jitter transfer function.
Acquisition T ime
T his is the transient time, measured in bit periods, required for
the AD807 to lock onto input data from its free-running state.
Symmetry—Recovered Clock Duty Cycle
Symmetry is calculated as (100
×
on time)/period, where on
time equals the time that the clock signal is greater than the
midpoint between its “0” level and its “1” level.
Bit E rror Rate vs. Signal-to-Noise Ratio
AD807 Bit Error Rate vs. Signal-to-Noise Ratio performance is
shown in Figure 11. Wideband amplitude noise is summed with
the input data signal as shown in Figure 4. Performance is
shown for input data levels of 5 mV and 10 mV.
BINARY
OUTPUT
EPITAXX ERM504
SCOPE
PROBE
AD807 QUANTIZER
V
CM
V
CM
2mVp-p
a. Single-Ended Input Application
BINARY
OUTPUT
AD8015
DIFFERENTIAL
OUTPUT TIA
SCOPE
PROBE
AD807 QUANTIZER
V
CM
V
CM
1mVp-p
+OUT
–OUT
b. Differential Input Application
Figure 3. (a–b) Single-Ended and Differential Input
Applications
DIFFERENTIAL
SIGNAL
SOURCE
∑
∑
POWER
SPLITTER
NOISE
SOURCE
FILTER
100MHz
D.U.T.
AD807
POWER COMBINER
+
POWER
COMBINER
+
50
0.47μF
75
100
1.0μF
GND
+5V
PIN
NIN
+
–
50
0.47μF
Figure 4. Bit Error Rate vs. Signal-to-Noise Ratio
Test: Block Diagram
400
400
AV
CC2
DIFFERENTIAL
INPUT
AV
EE
CURRENT SOURCES
HEADROOM
≥
0.7V
V
BE
ù
0.8V
0.5mA
1mA
0.5mA
a. Quantizer Differential Input Stage
5.9k
THRADJ
AV
EE
94.6k
1.2V +V
BE
b. Threshold Adjust
150
V
CC1
SDOUT
V
EE
I
OL
I
OH
150
c. Signal Detect Output (SDOUT)
450
450
V
CC2
DIFFERENTIAL
OUTPUT
V
EE
2.5mA
d. PLL Differential Output Stage—DATAOUT(N),
CLKOUT(N)
Figure 5. (a–d) Simplified Schematics
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