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參數(shù)資料
| 型號(hào)： | AD807 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming(帶數(shù)字轉(zhuǎn)換,時(shí)鐘恢復(fù)和重定時(shí)功能的光纖接收器) |
| 中文描述： | 光纖接收器與量化和時(shí)鐘恢復(fù)和數(shù)據(jù)重定時(shí)（帶數(shù)字轉(zhuǎn)換，時(shí)鐘恢復(fù)和重定時(shí)功能的光纖接收器） |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 234K |
| 代理商： | AD807 |
REV. A
–12–
AD807
USING T HE AD807
Ground Planes
Use of one ground plane for connections to both analog and
digital grounds is recommended.
Power Supply Connections
Use of a 10
μ
F capacitor between V
CC
and ground is recom-
mended. Care should be taken to isolate the +5 V power trace
to V
CC2
(Pin 3). T he V
CC2
pin is used inside the device to pro-
vide the CLK OUT and DAT AOUT signals.
Use of 0.1
μ
F capacitors between IC power supply and ground
is recommended. Power supply decoupling should take place as
close to the IC as possible. Refer to the schematic, Figure 21,
for recommended connections.
T ransmission Lines
Use of 50
transmission lines are recommended for PIN, NIN,
CLK OUT , and DAT AOUT signals.
T erminations
T ermination resistors should be used for PIN, NIN, CLK OUT ,
and DAT AOUT signals. Metal, thick film, 1% tolerance resistors
are recommended. T ermination resistors for the PIN, NIN sig-
nals should be placed as close as possible to the PIN, NIN pins.
Connections from +5 V to load resistors for PIN, NIN,
CLK OUT , and DAT AOUT signals should be individual, not
daisy chained. T his will avoid crosstalk on these signals.
Loop Damping Capacitor, C
D
A ceramic capacitor may be used for the loop damping capaci-
tor. Using a 0.15
μ
F, +20% capacitor for a damping factor of
five provides < 0.1 dB jitter peaking.
AD807 Output Squelch Circuit
A simple P-channel FET circuit can be used in series with the
Output Signal ECL Supply (V
CC2
, Pin 3) to squelch clock and
data outputs when SDOUT indicates a loss of signal (Figure
29). T he V
CC2
supply pin draws roughly 61 mA (14 mA for each
of 4 ECL loads, plus 5 mA for all 4 ECL output stages). T his
means that selection of a FET with ON RESIST ANCE of
0.5
will affect the common mode of the ECL outputs by only
31 mV.
1
2
5
6
7
3
4
8
16
15
12
11
10
14
13
9
V
EE
SDOUT
AV
CC2
PIN
NIN
AV
CC1
THRADJ
AV
EE
DATAOUTN
DATAOUTP
CLKOUTN
CLKOUTP
V
CC1
CF1
CF2
V
CC2
AD807
TO V
CC1
, AV
CC
, AV
CC2
P_FET
BYPASS
CAP
5V
Figure 29. Squelch Circuit Schematic
OUT LINE DIME NSIONS
Dimensions shown in inches and (mm).
16-Lead Small Outline IC Package
(R-16A)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
1
16
9
8
0.0500 (1.27)
0.0160 (0.41)
8
°
0
°
0.0196 (0.50)
0.0099 (0.25)
x 45
°
0.0099 (0.25)
0.0075 (0.19)
0.0192 (0.49)
0.0138 (0.35)
(1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
0.3937 (10.00)
0.3859 (9.80)
P
C
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