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參數(shù)資料
| 型號： | AD807 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming(帶數(shù)字轉(zhuǎn)換,時鐘恢復(fù)和重定時功能的光纖接收器) |
| 中文描述： | 光纖接收器與量化和時鐘恢復(fù)和數(shù)據(jù)重定時（帶數(shù)字轉(zhuǎn)換，時鐘恢復(fù)和重定時功能的光纖接收器） |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 234K |
| 代理商： | AD807 |
AD807
REV. A
–7–
RMS JITTER – Degrees
30
0
1.4
2.3
1.5
P
1.6
1.7
1.8
1.9
2.0
2.1
2.2
25
20
15
10
5
TEST CONDITIONS
WORST CASE:
– 40
°
C, 4.5V
Figure 12. Output J itter Histogram
FREQUENCY – Hz
1E+3
10010E+0
10E+6
100E+0
J
1E+3
10E+3
100E+3
1E+6
100E+0
10E+0
1E+0
AD807
SONET MASK
Figure 13. J itter Tolerance
NOISE – Vp-p @311MHz
3.0
0
0
0.2
J
0.4
0.6
0.8
1.0
2.0
1.0
PSR – NO FILTER
CMR
PSR – WITH FILTER
0.1
0.3
0.5
0.7
0.9
Figure 14. Output J itter vs. Supply Noise and
Output J itter vs. Common Mode Noise
T HE ORY OF OPE RAT ION
Quantizer
T he quantizer (comparator) has three gain stages, providing a
net gain of 350. T he quantizer takes full advantage of the Extra
Fast Complementary Bipolar (X FCB) process. T he input stage
uses a folded cascode architecture to virtually eliminate pulse
width distortion, and to handle input signals with common-
mode voltage as high as the positive supply. T he input offset
voltage is factory trimmed and guaranteed to be less than 500
μ
V.
X FCB’s dielectric isolation allows the different blocks within
this mixed-signal IC to be isolated from each other, hence the
2 mV Sensitivity is achieved. T raditionally, high speed compara-
tors are plagued by crosstalk between outputs and inputs, often
resulting in oscillations when the input signal approaches 10 mV.
T he AD807 quantizer toggles at
±
650
μ
V (1.3 mV sensitivity) at
the input without making bit errors. When the input signal is
lowered below
±
650
μ
V, circuit performance is dominated by
input noise, and not crosstalk.
12
11
6
14
13
3
AV
CC2
PIN
NIN
AV
CC1
V
CC1
V
CC2
AD807
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
500
500
309
50
50
0.1μF
3.65k
0.1μF
10μF
+5V
50
311MHz
NOISE
INPUT
0.1μF
QUANTIZER
INPUT
OPTIONAL FILTER
FERRITE BEAD
CHOKE
"BIAS TEE"
Figure 15. Power Supply Noise Sensitivity Test Circuit
12
11
6
14
13
3
AV
CC2
PIN
NIN
AV
CC1
V
CC1
V
CC2
AD807
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
500
500
309
50
50
0.1μF
3.65k
10μF
+5V
50
311MHz
NOISE
INPUT
0.1μF
QUANTIZER
INPUT
CHOKE
"BIAS TEE"
Figure 16. Common-Mode Rejection Test Circuit
Signal Detect
T he input to the signal detect circuit is taken from the first stage
of the quantizer. T he input signal is first processed through a
gain stage. T he output from the gain stage is fed to both a posi-
tive and a negative peak detector. T he threshold value is sub-
tracted from the positive peak signal and added to the negative
peak signal. T he positive and negative peak signals are then
compared. If the positive peak, POS, is more positive than the
negative peak, NEG, the signal amplitude is greater than the
threshold, and the output, SDOUT , will indicate the presence
of signal by remaining low. When POS becomes more negative
than NEG, the signal amplitude has fallen below the threshold,
and SDOUT will indicate a loss of signal (LOS) by going high.
T he circuit provides hysteresis by adjusting the threshold level
higher by a factor of two when the low signal level is detected.
T his means that the input data amplitude needs to reach twice
the set LOS threshold before SDOUT will signal that the data is
again valid. T his corresponds to a 3 dB optical hysteresis.
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