參數(shù)資料
型號： AD807
廠商： Analog Devices, Inc.
英文描述： Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming(帶數(shù)字轉(zhuǎn)換,時(shí)鐘恢復(fù)和重定時(shí)功能的光纖接收器)
中文描述： 光纖接收器與量化和時(shí)鐘恢復(fù)和數(shù)據(jù)重定時(shí)（帶數(shù)字轉(zhuǎn)換，時(shí)鐘恢復(fù)和重定時(shí)功能的光纖接收器）
文件頁數(shù)： 2/12頁
文件大?。?/td> 234K
代理商： AD807
AD807–SPECIFICATIONS
Parameter
QUANT IZER–DC CHARACT ERIST ICS
Input Voltage Range
Input Sensitivity, V
SENSE
Input Overdrive, V
OD
Input Offset Voltage
Input Current
Input RMS Noise
Input Pk-Pk Noise
QUANT IZER–AC CHARACT ERIST ICS
Upper –3 dB Bandwidth
Input Resistance
Input Capacitance
Pulse Width Distortion
LEVEL DET ECT
Level Detect Range
REV. A
–2–
Condition
Min
T yp
Max
Units
@ P
IN
or N
IN
P
IN
–N
IN
, Figure 1, BER =
≤
1
×
10
–10
Figure 1, BER =
≤
1
×
10
–10
2.5
2
0.001
V
S
V
mV
V
μ
V
μ
A
μ
V
μ
V
2.5
500
10
50
5
50
650
BER =
≤
1
×
10
–10
BER =
≤
1
×
10
–10
180
1
2
100
MHz
M
pF
ps
R
T HRESH
= INFINIT E
R
T HRESH
= 49.9 k
R
T HRESH
= 3.4 k
DC Coupled
R
T HRESH
= INFINIT E
R
T HRESH
= 49.9 k
R
T HRESH
= 3.4 k
Load = +4 mA
Load = –1.2 mA
0.8
4
14
0.1
2.3
3.0
3.0
3.6
2
5
20
4.0
7.4
25
1.5
10.0
9.0
10.0
mV
mV
mV
μ
s
dB
dB
dB
V
V
Response T ime
Hysteresis (Electrical)
4.0
5.0
7.0
SDOUT Output Logic High
SDOUT Output Logic Low
PHASE-LOCK ED LOOP NOMINAL
CENT ER FREQUENCY
CAPT URE RANGE
T RACK ING RANGE
ST AT IC PHASE ERROR
SET UP T IME (t
SU
)
HOLD T IME (t
H
)
PHASE DRIFT
JIT T ER
0.4
155.52
MHz
MHz
MHz
Degrees
ns
ns
Degrees
Degrees RMS
Degrees RMS
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
155
155
156
156
20
3.5
3.3
40
2
7
–1 PRN Sequence
Figure 2
Figure 2
240 Bits, No T ransitions
2
7
–1 PRN Sequence
2
23
–1 PRN Sequence
f = 10 Hz
f = 6.5 kHz
f = 65 kHz
f = 1.3 MHz
4
3.2
3.1
3.0
3.0
2.0
2.0
3000
7.6
1.0
0.67
2.7
JIT T ER T OLERANCE
4.5
0.45
0.45
JIT T ER T RANSFER
Peaking (Figure 20)
C
D
= 0.15
μ
F
C
D
= 0.33
μ
F
0.08
0.04
92
dB
dB
kHz
Bandwidth
Acquisition T ime
C
D
= 0.1
μ
F
C
D
= 0.33
μ
F
POWER SUPPLY VOLT AGE
POWER SUPPLY CURRENT
65
130
2
23
–1 PRN Sequence, T
A
= +25
°
C
V
CC
= 5 V, V
EE
= GND
V
MIN
to V
MAX
V
CC
= 5.0 V, V
EE
= GND,
T
A
= +25
°
C
4
×
10
5
2
×
10
6
2
×
10
6
Bit Periods
Bit Periods
Volts
4.5
5.5
25
34.5
39.5
mA
PECL OUT PUT VOLT AGE LEVELS
Output Logic High, V
OH
Output Logic Low, V
OL
SYMMET RY (Duty Cycle)
Recovered Clock Output, Pin 5
OUT PUT RISE / FALL T IMES
Rise T ime (t
R
)
Fall T ime (t
F
)
Specifications subject to change without notice.
–1.2
–2.0
–1.0
–1.8
–0.7
–1.7
Volts
Volts
Referenced to V
CC
ρ
= 1/2, T
A
= +25
°
C,
V
CC
= 5 V, V
EE
= GND
50.1
54.1
%
20%–80%
80%–20%
1.1
1.1
1.5
1.5
ns
ns
(T
A
= T
MN
to T
MAX
, V
S
= V
MN
to V
MAX
, C
D
= 0.1
m
F, unless otherwse noted)
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