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參數(shù)資料
| 型號： | AD7923BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 4CH W/SEQ 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 7.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極 |
| 其它名稱： | AD7923BRUZ-REEL7DKR |
Data Sheet
AD7923
Rev. D | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DIN
CS
AGND
REFIN
AVDD
SCLK
VDRIVE
DOUT
AGND
VIN2
AGND
VIN3
VIN1
VIN0
AGND
AD7923
TOP VIEW
(Not to Scale)
03086-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No.
Mnemonic
Function
1
SCLK
Serial Clock. Logic Input. SCLK provides the serial clock for accessing data for the part. This clock input is also used
as the clock source for the AD7923 conversion process.
2
DIN
Data In. Logic Input. Data to be written to the control register is provided on this input and is clocked into the
register on the falling edge of SCLK (see the Control Register Descriptions section).
3
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7923
and framing the serial data transfer.
4, 8,
13, 16
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7923. All analog input signals and any
external reference signal should be referred to this AGND voltage. All AGND pins should be connected together.
5, 6
AVDD
Analog Power Supply Input. The AVDD range for the AD7923 is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN range,
AVDD should be from 4.75 V to 5.25 V.
7
REFIN
Reference Input for the AD7923. An external reference must be applied to this input. The voltage range for the
external reference is 2.5 V ± 1% for specified performance.
12 to 9
VIN0 to VIN3
Analog Input 0 through Analog Input 3. Four single-ended analog input channels that are multiplexed into the on-
chip track-and-hold. The analog input channel to be converted is selected by using the Address Bits ADD1 and
ADD0 of the control register. The address bits in conjunction with the SEQ1 and SEQ0 bits allow the sequencer to
be programmed. The input range for all input channels can extend from 0 V to REFIN or from 0 V to 2 × REFIN as
selected via the range bit in the control register. Any unused input channels must be connected to AGND to avoid
noise pickup.
14
DOUT
Data Out. Logic Output. The conversion result from the AD7923 is provided on this output pin as a serial data
stream. The AD7923 serial data stream consists of two leading 0s, and two address bits indicating which channel
the conversion result corresponds to, followed by 12 bits of conversion data, MSB first. The output coding can be
selected as straight binary or twos complement via the coding bit in the control register. The data bits are clocked
out of the AD7923 on the SCLK falling edge.
15
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at which voltage the serial interface
operates.
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