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參數(shù)資料
| 型號： | AD7923BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 4CH W/SEQ 16TSSOP |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 7.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 4 個單端，單極 |
| 其它名稱： | AD7923BRUZ-REEL7DKR |
Data Sheet
AD7923
Rev. D | Page 19 of 24
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DIN LINE HIGH FOR FIRST DUMMY CONVERSION
DATA INTO CONTROL REGISTER
TO KEEP THE PART IN NORMAL MODE, LOAD
PM1 = PM0 = 1 IN CONTROL REGISTER
1
14
16
1
14
16
ALLOW
tPOWER TO ELAPSE
IF IN SHUTDOWN AT POWER-ON
PART BEGINS TO POWER UP ON
CS RISING EDGE AS PM1 = PM0 = 1
PART IS IN
UNKNOWN MODE
AFTER POWER-ON
CS
SCLK
DOUT
DIN
03086-023
t12
Figure 23. Placing the AD7923 into Normal Mode after Supplies are First Applied
INVALID DATA
1
14
16
PART ENTERS SHUTDOWN ON
CS RISING EDGE AS PM1 = PM0 = 0
PART IS IN
UNKNOWN MODE
AFTER POWER-ON
CS
SCLK
DOUT
DIN
DATA INTO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON
THE FIRST 12 CLOCKS. PM1 = 1, PM0 = 0
03086-024
Figure 24. Placing the AD7923 into Full Shutdown Mode after Supplies are First Applied
INVALID DATA
DIN LINE HIGH FOR FIRST DUMMY CONVERSION
DATA INTO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS. PM1 = 0, PM0 = 1
1
14
16
1
14
16
PART IS IN
UNKNOWN MODE
AFTER POWER-ON
CS
SCLK
DOUT
DIN
03086-025
PART ENTERS AUTO SHUTDOWN ON
CS RISING EDGE AS PM1 = 0, PM0 = 1
Figure 25. Placing the AD7923 into Auto Shutdown Mode after Supplies are First Applied
POWER vs. THROUGHPUT RATE
In auto shutdown mode, the average power consumption of the
ADC can be reduced at any given throughput rate. The power
saving depends on the SCLK frequency used, that is, conversion
time. In some cases where the conversion time is a large propor-
tion of the cycle time, the throughput rate needs to be reduced
to take advantage of the power-down modes. Assuming a
20 MHz SCLK is used, the conversion time is 800 ns, but the
cycle time is 5 μs when the sampling rate is at a maximum of
200 kSPS. If the AD7923 is placed into shutdown for the
remainder of the cycle time, then on average far less power is
consumed in every cycle compared to leaving the device in
normal mode. Furthermore, Figure 26 shows how, as the
throughput rate is reduced, the part remains in its shutdown
longer and the average power consumption drops accordingly
over time.
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