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| 型號： | AD7711AARZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT RTD I SOURCE 24SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 1.03k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 52.5mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個差分，單極；2 個差分，雙極 |
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2
AD7711A
–17–
REV. D
USING THE AD7711A
SYSTEM DESIGN CONSIDERATIONS
The AD7711A operates differently from successive approxima-
tion ADCs or integrating ADCs. Since it samples the signal
continuously, like a tracking ADC, there is no need for a start
convert command. The output register is updated at a rate
determined by the first notch of the filter, and the output can be
read at any time, either synchronously or asynchronously.
Clocking
The AD7711A requires a master clock input, which may be an
external TTL/CMOS compatible clock signal applied to the
MCLK IN pin with the MCLK OUT pin left unconnected.
Alternatively, a crystal of the correct frequency can be con-
nected between MCLK IN and MCLK OUT, in which case the
clock circuit will function as a crystal controlled oscillator. For
lower clock frequencies, a ceramic resonator may be used instead
of the crystal. For these lower frequency oscillators, external
capacitors may be required on either the ceramic resonator or
on the crystal.
The input sampling frequency, the modulator sampling fre-
quency, the –3 dB frequency, the output update rate, and the
calibration time are all directly related to the master clock fre-
quency, fCLK IN. Reducing the master clock frequency by a factor
of 2 will halve the above frequencies and update rate and will
double the calibration time.
The current drawn from the DVDD power supply is also directly
related to fCLK IN. Reducing fCLK IN by a factor of 2 will halve the
DVDD current but will not affect the current drawn from the
AVDD power supply.
System Synchronization
If multiple AD7711As are operated from a common master
clock, they can be synchronized to update their output registers
simultaneously. A falling edge on the
SYNC input resets the
filter and places the AD7711A into a consistent, known state. A
common signal to the AD7711As’
SYNC inputs will synchro-
nize their operation. This would normally be done after each
AD7711A has performed its own calibration or has had calibra-
tion coefficients loaded to it.
The
SYNC input can also be used to reset the digital filter in
systems where the turn-on time of the digital power supply
(DVDD) is very long. In such cases, the AD7711A will start
operating internally before the DVDD line has reached its mini-
mum operating level, 4.75 V. With a low DVDD voltage, the
AD7711A’s internal digital filter logic does not operate cor-
rectly. Thus, the AD7711A may have clocked itself into an
incorrect operating condition by the time that DVDD has
reached its correct level. The digital filter will be reset upon
issue of a calibration command (whether it is self-calibration,
system calibration, or background calibration) to the AD7711A.
This ensures correct operation of the AD7711A. In systems
where the power-on default conditions of the AD7711A are
acceptable, and no calibration is performed after power-on,
issuing a
SYNC pulse to the AD7711A will reset the AD7711A’s
digital filter logic. An R, C on the
SYNC line, with R, C time
constant longer than the DVDD power-on time, will perform the
SYNC function.
Accuracy
Sigma-delta ADCs, like VFCs and other integrating ADCs, do
not contain any source of nonmonotonicity and inherently offer
no missing codes performance. The AD7711A achieves excel-
lent linearity by the use of high quality, on-chip silicon dioxide
capacitors, which have a very low capacitance/voltage coeffi-
cient. The device also achieves low input drift through the use
of chopper stabilized techniques in its input stage. To ensure
excellent performance over time and temperature, the AD7711A
uses digital calibration techniques that minimize offset and
gain error.
Autocalibration
Autocalibration on the AD7711A removes offset and gain errors
from the device. A calibration routine should be initiated on the
device whenever there is a change in the ambient operating
temperature or supply voltage. It should also be initiated if there
is a change in the selected gain, filter notch, or bipolar/unipolar
input range. However, if the AD7711A is in its background
calibration mode, the above changes are all automatically taken
care of (after allowing for the settling time of the filter).
The AD7711A offers self-calibration, system calibration, and
background calibration facilities. For calibration to occur on the
selected channel, the on-chip microcontroller must record the
modulator output for two different input conditions. These are
zero-scale and full-scale points. With these readings, the
microcontroller can calculate the gain slope for the input to
output transfer function of the converter. Internally, the part
works with a resolution of 33 bits to determine its conversion
result of either 16 bits or 24 bits.
The AD7711A also provides the facility to write to the on-chip
calibration registers, and, in this manner, the span and offset for
the part can be adjusted by the user. The offset calibration regis-
ter contains a value that is subtracted from all conversion results,
while the full-scale calibration register contains a value that is
multiplied by all conversion results. The offset calibration coeffi-
cient is subtracted from the result prior to the multiplication by
the full-scale coefficient. In the first three modes outlined here,
the
DRDY line indicates that calibration is complete by going
low. If
DRDY is low before (or goes low during) the calibration
command, it may take up to one modulator cycle before
DRDY
goes high to indicate that calibration is in progress. Therefore,
DRDY should be ignored for up to one modulator cycle after
the last bit of the calibration command is written to the control
register.
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| AD7711AN | 功能描述:IC ADC 24BIT RTD I SOURCE 24-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD7711ANZ | 功能描述:IC ADC 24BIT RTD I SOURCE 24-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7711ANZ | 制造商:Analog Devices 功能描述:IC ADC 24-BIT SIGMA DELTA |
| AD7711AQ | 功能描述:IC ADC 24BIT RTD I SOURCE 24CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7711AR | 功能描述:IC ADC 24BIT RTD I SOURCE 24SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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