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| 型號： | AD7711AARZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT RTD I SOURCE 24SOIC |
| 標準包裝： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 1.03k |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 52.5mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個差分，單極；2 個差分，雙極 |
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REV. D
AD7711A
–16–
Bipolar/Unipolar Inputs
The two analog inputs on the AD7711A can accept either uni-
polar or bipolar input voltage ranges. Bipolar or unipolar
options are chosen by programming the B/U bit of the control
register. This programs both channels for either unipolar or
bipolar operation. Programming the part for either unipolar or
bipolar operation does not change any of the input signal condi-
tioning; it simply changes the data output coding. The data coding
is binary for unipolar inputs and offset binary for bipolar inputs.
The input channels are differential and, as a result, the voltage
to which the unipolar and bipolar signals are referenced is the
voltage on the AIN(–) input. For example, if AIN(–) is +1.25 V
and the AD7711A is configured for unipolar operation with a
gain of 1 and a VREF of 2.5 V, the input voltage range on the
AIN(+) input is 1.25 V to 3.75 V. If AIN(–) is 1.25 V and the
AD7711A is configured for bipolar mode with a gain of 1 and
a VREF of 2.5 V, the analog input range on the AIN(+) input is
–1.25 V to +3.75 V.
REFERENCE INPUT/OUTPUT
The AD7711A contains a temperature compensated 2.5 V
reference, which has an initial tolerance of
±1%. This reference
voltage is provided at the REF OUT pin and can be used as the
reference voltage for the part by connecting the REF OUT pin
to the REF IN(+) pin. This REF OUT pin is a single-ended
output, referenced to AGND, that is capable of providing up to
1 mA to an external load. In applications where REF OUT is
connected to REF IN(+), REF IN(–) should be tied to AGND
to provide the nominal 2.5 V reference for the AD7711A.
The reference inputs of the AD7711A, REF IN(+) and REF
IN(–), provide a differential reference input capability. The
common-mode range for these differential inputs is from VSS to
AVDD. The nominal differential voltage, VREF (REF IN(+) –
REF IN(–)), is 2.5 V for specified operation, but the reference
voltage can go to 5 V with no degradation in performance provided
that the absolute value of REF IN(+) and REF IN(–) does not
exceed its AVDD and VSS limits and the VBIAS input voltage range
limits are obeyed. The part is also functional with VREF voltages
down to 1 V but with degraded performance as the output noise
will, in terms of LSB size, be larger. REF IN(+) must always be
greater than REF IN(–) for correct operation of the AD7711A.
Both reference inputs provide a high impedance, dynamic load
similar to the analog inputs. The maximum dc input leakage
current is 10 pA (
±1 nA over temperature), and source resis-
tance may result in gain errors on the part. The reference inputs
look like the analog input (see Figure 7). In this case, RINT is
5 k
W typ and CINT varies with gain. The input sample rate is
fCLK IN/256 and does not vary with gain. For gains of 1 to 8,
CINT is 20 pF; for a gain of 16, it is 10 pF; for a gain of 32, it is
5 pF; for a gain of 64, it is 2.5 pF; and for a gain of 128, it is
1.25 pF.
The digital filter of the AD7711A removes noise from the refer-
ence input just as it does with the analog input, and the same
limitations apply regarding lack of noise rejection at integer
multiples of the sampling frequency. The output noise perfor-
mance outlined in Tables I and II assumes a clean reference.
If the reference noise in the bandwidth of interest is excessive, it
can degrade the performance of the AD7711A. Using the on-
chip reference as the reference source for the part (i.e., connect-
ing REF OUT to REF IN) results in somewhat degraded output
noise performance from the AD7711A for portions of the noise
table that are dominated by the device noise. The on-chip
reference noise effect is eliminated in ratiometric applications
where the reference is used to provide the excitation voltage for
the analog front end. The connection scheme shown in Figure 8
is recommended when using the on-chip reference. Recom-
mended reference voltage sources for the AD7711A include the
AD780 and AD680 2.5 V references.
AD7711A
REF OUT
REF IN(+)
REF IN(–)
Figure 8. REF OUT/REF IN Connection
VBIAS Input
The VBIAS input determine at what voltage the internal analog
circuitry is biased. It essentially provides the return path for
analog currents flowing in the modulator and, as such, it should
be driven from a low impedance point to minimize errors.
For maximum internal headroom, the VBIAS voltage should be
set halfway between AVDD and VSS. The difference between
AVDD and (VBIAS + 0.85
VREF) determines the amount of
headroom the circuit has at the upper end, while the difference
between VSS and (VBIAS – 0.85
VREF) determines the amount
of headroom the circuit has at the lower end. Care should be
taken in choosing a VBIAS voltage to ensure that it stays within
prescribed limits. For single +5 V operation, the selected VBIAS
voltage must ensure that VBIAS
± 0.85 VREF does not exceed
AVDD or VSS or that the VBIAS voltage itself is greater than VSS
+ 2.1 V and less than AVDD – 2.1 V. For single +10 V operation
or dual
±5 V operation, the selected VBIAS voltage must ensure
that VBIAS
± 0.85 VREF does not exceed AVDD or VSS or that
the VBIAS voltage itself is greater than VSS + 3 V or less than
AVDD –3 V. For example, with AVDD = 4.75 V, VSS = 0 V
and VREF = 2.5 V, the allowable range for the VBIAS voltage is
2.125 V to 2.625 V. With AVDD = 9.5 V, VSS = 0 V and VREF =
5 V, the range for VBIAS is 4.25 V to 5.25 V. With AVDD =
+4.75 V, VSS = –4.75 V, and VREF = +2.5 V, the VBIAS range
is –2.625 V to +2.625 V.
The VBIAS voltage does have an effect on the AVDD power sup-
ply rejection performance of the AD7711A. If the VBIAS voltage
tracks the AVDD supply, it improves the power supply rejection
from the AVDD supply line from 80 dB to 95 dB. Using an
external Zener diode connected between the AVDD line and
VBIAS as the source for the VBIAS voltage gives the improvement
in AVDD power supply rejection performance.
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