參數(shù)資料
型號(hào)： AD7711AARZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT RTD I SOURCE 24SOIC
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 24
采樣率（每秒）： 1.03k
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 52.5mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 管件
輸入數(shù)目和類型： 2 個(gè)差分，單極；2 個(gè)差分，雙極
REV. D
AD7711A
–12–
Figures 2a and 2b give information similar to that outlined in Table I. In these plots, the output rms noise is shown for the full
range of available cutoffs frequencies rather than for some typical cutoff frequencies as in Tables I and II. The numbers given in
these plots are typical values at 25
∞C.
NOTCH FREQUENCY – Hz
10000
1000
0.1
10
10000
100
OUTPUT
NOISE
–
V
1000
100
10
1
GAIN OF 1
GAIN OF 2
GAIN OF 4
GAIN OF 8
Figure 2a. Plot of Output Noise vs. Gain and Notch
Frequency (Gains of 1 to 8)
CIRCUIT DESCRIPTION
The AD7711A is a sigma-delta A/D converter with on-chip
digital filtering, intended for the measurement of wide dynamic
range, low frequency signals such as those in weigh scale, indus-
trial control, or process control applications. It contains a sigma-
delta (or charge balancing) ADC, a calibration microcontroller
with on-chip static RAM, a clock oscillator, a digital filter, and a
bidirectional serial communications port.
The part contains two programmable gain differential analog
input channels. The gain range is from 1 to 128, allowing the
part to accept unipolar signals of between 0 mV and 20 mV and
0 V and 2.5 V or bipolar signals in the range from
±20 mV to
±2.5 V when the reference input voltage equals 2.5 V. The
input signal to the selected analog input channel is continu-
ously sampled at a rate determined by the frequency of the
master clock, MCLK IN, and the selected gain (see Table
III). A charge-balancing A/D converter (sigma-delta modulator)
converts the sampled signal into a digital pulse train whose duty
cycle contains the digital information. The programmable gain
function on the analog input is also incorporated in this sigma-
delta modulator with the input sampling frequency being modi-
fied to give the higher gains. A sinc
3 digital low-pass filter
processes the output of the sigma-delta modulator and updates
the output register at a rate determined by the first notch fre-
quency of this filter. The output data can be read from the serial
port randomly or periodically at any rate up to the output regis-
ter update rate. The first notch of this digital filter (and there-
fore its –3 dB frequency) can be programmed via an on-chip
control register. The programmable range for this first notch
frequency is from 9.76 Hz to 1.028 kHz, giving a programmable
range for the –3 dB frequency of 2.58 Hz to 269 Hz.
NOTCH FREQUENCY – Hz
10000
1000
0.1
10
10000
100
OUTPUT
NOISE
–
V
1000
100
10
1
GAIN OF 16
GAIN OF 32
GAIN OF 128
GAIN OF 64
Figure 2b. Plot of Output Noise vs. Gain and Notch
Frequency (Gains of 16 to 128)
The basic connection diagram for the part is shown in Figure 3.
This shows the AD7711A in the external clocking mode with
both the AVDD and DVDD pins of the AD7711A being driven
from the analog 5 V supply. Some applications will have
separate supplies for both AVDD and DVDD, and in some of
these cases, the analog supply will exceed the 5 V digital supply
(see the Power Supplies and Grounding section).
ANALOG
5V SUPPLY
10 F
0.1 F
AVDD DVDD
AIN1(+)
AIN1(–)
AGND
VSS
DGND
REF OUT
REF IN(+)
VBIAS
REF IN(–)
RTD CURRENT
DRDY
TFS
RFS
SDATA
SCLK
A0
MODE
SYNC
MCLK OUT
MCLK IN
AD7711A
DIFFERENTIAL
ANALOG INPUT
DIFFERENTIAL
ANALOG INPUT
ANALOG GROUND
DIGITAL GROUND
DATA READY
TRANSIT (WRITE)
RECEIVE (READ)
SERIAL DATA
SERIAL CLOCK
ADDRESS INPUT
5V
AIN2(+)
AIN2(–)
Figure 3. Basic Connection Diagram
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