參數(shù)資料
型號(hào)： AD7711AARZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/28頁(yè)
文件大小： 0K
描述： IC ADC 24BIT RTD I SOURCE 24SOIC
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 24
采樣率（每秒）： 1.03k
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 52.5mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 管件
輸入數(shù)目和類型： 2 個(gè)差分，單極；2 個(gè)差分，雙極
REV. D
AD7711A
–20–
DIGITAL INTERFACE
The AD7711A’s serial communications port provides a flexible
arrangement to allow easy interfacing to industry-standard
microprocessors, microcontrollers, and digital signal processors.
A serial read to the AD7711A can access data from the output
register, the control register, or the calibration registers. A serial
write to the AD7711A can write data to the control register or
the calibration registers.
Two different modes of operation are available, optimized for
different types of interfaces where the AD7711A can act either
as master in the system (it provides the serial clock) or as slave
(an external serial clock can be provided to the AD7711A).
These two modes, labeled self-clocking mode and external clock-
ing mode, are discussed in detail in the following sections.
Self-Clocking Mode
The AD7711A is configured for its self-clocking mode by tying
the MODE pin high. In this mode, the AD7711A provides the
serial clock signal used for the transfer of data to and from the
AD7711A. This self-clocking mode can be used with processors
that allow an external device to clock their serial port, including
most digital signal processors and microcontrollers such as the
68HC11 and 68HC05. It also allows easy interfacing to serial
parallel conversion circuits in systems with parallel data commu-
nication, allowing interfacing to 74XX299 universal shift regis-
ters without any additional decoding. In the case of shift registers,
the serial clock line should have a pull-down resistor instead of
the pull-up resistor shown in Figure 10 and Figure 11.
Read Operation
Data can be read from the output register, the control register,
or the calibration registers. A0 determines whether the data read
accesses data from the control register or from the output/cali-
bration registers. This A0 signal must remain valid for the dura-
tion of the serial read operation. With A0 high, data is accessed
from either the output register or from the calibration registers.
With A0 low, data is accessed from the control register.
The function of the
DRDY line is dependent on only the output
update rate of the device and the reading of the output data
register.
DRDY goes low when a new data-word is available in
the output data register. It is reset high when the last bit of data
(either 16th bit or 24th bit) is read from the output register. If
data is not read from the output register, the
DRDY line will
remain low. The output register will continue to be updated at
the output update rate, but
DRDY will not indicate this. A read
from the device in this circumstance will access the most recent
word in the output register. If a new data-word becomes avail-
able to the output register while data is being read from the
output register,
DRDY will not indicate this and the new data-
word will be lost to the user.
DRDY is not affected by reading
from the control register or the calibration registers.
Data can be accessed from the output data register only when
DRDY is low. If RFS goes low with DRDY high, no data trans-
fer will take place.
DRDY does not have any effect on reading
data from the control register or from the calibration registers.
Figure 10 shows a timing diagram for reading from the AD7711A
in the self-clocking mode. This read operation shows a read
from the AD7711A’s output data register. A read from the
control register or calibration registers is similar but, in these
cases, the
DRDY line is not related to the read function.
Depending on the output update rate, it can go low at any stage
in the control/calibration register read cycle without affecting
the read and its status should be ignored. A read operation from
either the control or calibration register must always read 24 bits
of data from the respective register.
Figure 10 shows a read operation from the AD7711A. For the
timing diagram shown, it is assumed that there is a pull-up
resistor on the SCLK output. With
DRDY low, the RFS input
is brought low.
RFS going low enables the serial clock of the
AD7711A and also places the MSB of the word on the serial
data line. All subsequent data bits are clocked out on a high to
low transition of the serial clock and are valid prior to the fol-
lowing rising edge of this clock. The final active falling edge
of SCLK clocks out the LSB, and this LSB is valid prior to
the final active rising edge of SCLK. Coincident with the next
falling edge of SCLK,
DRDY is reset high. DRDY going high
turns off the SCLK and the SDATA outputs, which means that
the data hold time for the LSB is slightly shorter than for all
other bits.
t3
t5
t9
t8
t6
t4
t2
t7
t10
MSB
LSB
THREE-STATE
SDATA (O)
SCLK (O)
RFS (I)
A0 (I)
DRDY (O)
Figure 10. Self-Clocking Mode, Output Data Read Operation
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