參數(shù)資料
型號(hào)： AD7710SQ
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： Signal Conditioning ADC
中文描述： 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP24
封裝： 0.300 INCH, HERMETIC SEALED, CERDIP-24
文件頁數(shù)： 3/28頁
文件大?。?/td> 220K
代理商： AD7710SQ
Parameter
A, S Versions
1
Units
Conditions/Comments
REFERENCE OUTPUT
Output Voltage
Initial Tolerance @ +25
°
C
Drift
Output Noise
Line Regulation (AV
DD
)
Load Regulation
External Current
V
BIAS
INPUT
12
Input Voltage Range
2.5
±
1
20
30
1
1.5
1
V nom
% max
ppm/
°
C typ
μ
V typ
mV/V max
mV/mA max Maximum Load Current 1 mA
mA max
pk-pk Noise 0.1 Hz to 10 Hz Bandwidth
AV
DD
– 0.85
×
V
REF
or AV
DD
– 3.5
See V
BIAS
Input Section
Whichever Is Smaller: +5 V/–5 V or +10 V/0 V
Nominal AV
DD
/V
SS
Whichever Is Smaller; +5 V/0 V Nominal AV
DD
/V
SS
See V
BIAS
Input Section
Whichever Is Greater; +5 V/–5 V or +10 V/0 V
Nominal AV
DD
/V
SS
Whichever Is Greater; +5 V/0 V Nominal AV
DD
/V
SS
Increasing with Gain
V max
or AV
DD
– 2.1
V
SS
+ 0.85
×
V
REF
or V
SS
+ 3
V max
V min
or V
SS
+ 2.1
65 to 85
V min
dB typ
V
BIAS
Rejection
LOGIC INPUTS
Input Current
All Inputs Except MCLK IN
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
MCLK IN Only
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
LOGIC OUTPUTS
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
13
±
10
μΑ
max
0.8
2.0
V max
V min
0.8
3.5
V max
V min
0.4
DV
DD
– 1
±
10
9
V max
V min
μ
A max
pF typ
I
SINK
= 1.6 mA
I
SOURCE
= 100
μ
A
TRANSDUCER BURNOUT
Current
Initial Tolerance @ +25
°
C
Drift
4.5
±
10
0.1
μ
A nom
%
typ
%/
°
C typ
COMPENSATION CURRENT
Output Current
Initial Tolerance @ +25
°
C
Drift
Line Regulation (AV
DD
)
Load Regulation
Output Compliance
20
±
4
35
20
20
AV
DD
– 2
μ
A nom
μ
A max
ppm/
°
C typ
nA/V max
nA/V max
V max
AV
DD
= +5 V
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit
l4
Negative Full-Scale Calibration Limit
l4
Offset Calibration Limits
15
Input Span
15
(1.05
×
V
REF
)/GAIN
–(1.05
×
V
REF
)/GAIN
–(1.05
×
V
REF
)/GAIN
0.8
×
V
REF
/GAIN
(2.1
×
V
REF
)/GAIN
V max
V max
V max
V min
V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
NOTES
12
The AD7710 is tested with the following V
BIAS
voltages. With AV
DD
= +5 V and V
SS
= 0 V, V
BIAS
= +2.5 V; with AV
DD
= +10 V and V
SS
= 0 V, V
BIAS
= +5 V and
with AV
DD
= +5 V and V
SS
= –5 V, V
BIAS
= 0 V.
13
Guaranteed by design, not production tested.
14
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale then the device will
output all 0s.
15
These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV
DD
+ 30 mV or go more negative than V
SS
– 30 mV.
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
REV. F
–3–
AD7710
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7710SQ/883B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 24-Bit
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