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參數(shù)資料
| 型號(hào)： | AD7710SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Signal Conditioning ADC |
| 中文描述： | 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP24 |
| 封裝： | 0.300 INCH, HERMETIC SEALED, CERDIP-24 |
| 文件頁(yè)數(shù)： | 2/28頁(yè) |
| 文件大?。?/td> | 220K |
| 代理商： | AD7710SQ |
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REV. F
–2–
Parameter
STATIC PERFORMANCE
No Missing Codes
A, S Versions
1
Units
Conditions/Comments
24
22
18
15
12
Tables I and II
±
0.0015
±
0.003
See Note 4
1
0.3
See Note 4
0.5
0.25
See Note 4
0.5
0.25
2
Bits min
Bits min
Bits min
Bits min
Bits min
Guaranteed by Design. For Filter Notches
≤
60 Hz
For Filter Notch = 100 Hz
For Filter Notch = 250 Hz
For Filter Notch = 500 Hz
For Filter Notch = 1 kHz
Depends on Filter Cutoffs and Selected Gain
Filter Notches
≤
60 Hz
Typically
±
0.0003%
Excluding Reference
Excluding Reference. For Gains of 1, 2
Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
Output Noise
Integral Nonlinearity @ +25
°
C
T
MIN
to T
MAX
Positive Full-Scale Error
2,
3
Full-Scale Drift
5
% of FSR max
% of FSR max
μ
V/
°
C typ
μ
V/
°
C typ
Unipolar Offset Error
2
Unipolar Offset Drift
5
μ
V/
°
C typ
μ
V/
°
C typ
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
Bipolar Zero Error
2
Bipolar Zero Drift
5
μ
V/
°
C typ
μ
V/
°
C typ
ppm/
°
C typ
% of FSR max
% of FSR max
μ
V/
°
C typ
μ
V/
°
C typ
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
Gain Drift
Bipolar Negative Full-Scale Error
2
@ +25
°
C
±
0.003
T
MIN
to T
MAX
Bipolar Negative Full-Scale Drift
5
Excluding Reference
Typically
±
0.0006%
Excluding Reference. For Gains of 1, 2
Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
±
0.006
1
0.3
ANALOG INPUTS/REFERENCE INPUTS
Input Common-Mode Rejection (CMR)
100
90
V
SS
to AV
DD
100
100
150
150
10
1
20
dB min
dB min
V min to V max
dB min
dB min
dB min
dB min
pA max
nA max
pF max
At DC and AV
DD
= 5 V
At DC and AV
DD
= 10 V
Common-Mode Voltage Range
6
Normal-Mode 50 Hz Rejection
7
Normal-Mode 60 Hz Rejection
7
Common-Mode 50 Hz Rejection
7
Common-Mode 60 Hz Rejection
7
DC Input Leakage Current
7
@ +25
°
C
T
MIN
to T
MAX
Sampling Capacitance
7
Analog Inputs
8
Input Voltage Range
9
For Filter Notches of 10, 25, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 10, 30, 60 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 10, 25, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 10, 30, 60 Hz,
±
0.02
×
f
NOTCH
For Normal Operation. Depends on Gain Selected
Unipolar Input Range (B/U Bit of Control Register = 1)
Bipolar Input Range (B/U Bit of Control Register = 0)
0 to +V
REF10
±
V
REF
See Table III
nom
nom
Input Sampling Rate, f
S
Reference Inputs
REF IN(+) – REF IN(–) Voltage
11
+2.5 to +5
V min to V max For Specified Performance. Part Is Functional with
Lower V
REF
Voltages
Input Sampling Rate, f
S
NOTES
Temperature ranges are as follows: A Version, –40
°
C to +85
°
C; S Version, –55
°
C to +125
°
C. See also Note 16.
2
Applies after calibration at the temperature of interest.
3
Positive full-scale error applies to both unipolar and bipolar input ranges.
4
These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20
μ
V typical after self-calibration
or background calibration.
5
Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
6
This common-mode voltage range is allowed provided that the input voltage on AIN(+) and AIN(–) does not exceed AV
DD
+ 30 mV and V
SS
– 30 mV.
7
These numbers are guaranteed by design and/or characterization.
8
The analog inputs present a very high impedance dynamic load which varies with clock frequency and input sample rate. The maximum recommended source
resistance depends on the selected gain (see Tables IV and V).
9
The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs. The absolute
voltage on the analog inputs should not go more positive than AV
DD
+ 30 mV or go more negative than V
SS
– 30 mV.
10
V
REF
= REF IN(+) – REF IN(–).
11
The reference input voltage range may be restricted by the input voltage range requirement on the V
BIAS
input.
f
CLK IN
/256
AD7710–SPECIFICATIONS
(AV
DD
= +5V
6
5%; DV
DD
= +5V
6
5%; V
SS
= 0V or –5 V
6
5%; REF IN(+) = +2.5V;
REFIN(–) = AGND; MCLK IN = 10MHz unless otherwise noted. All specifications T
MIN
to T
MAX
unless otherwise noted.)
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