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參數(shù)資料
| 型號： | AD7450BRZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT DIFF IN 1MSPS 8SOIC |
| 標準包裝： | 98 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 9.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
| 配用： | EVAL-AD7450CBZ-ND - BOARD EVALUATION FOR AD7450 |
–16–
AD7450
1
2
345
13
16
15
14
00
0
DB11
DB10
DB2
DB1
DB0
t
2
4 LEADING ZEROS
t
8
t
QUIET
t
CONVERT
B
CS
SCLK
SDATA
t
6
t
7
t
4
t
5
t
3
t
1
THREE-STATE
Figure 19. Serial Interface Timing Diagram
1
2
345
13
16
15
14
t
CONVERT
B
CS
t
ACQ
12.5(1/fSCLK)
1/THROUGHPUT
10ns
SCLK
C
t
QUIET
t2
t5
t6
t8
Figure 20. Serial Interface Timing Example
MODES OF OPERATION
The mode of operation of the AD7450 is selected by controlling
the logic state of the
CS signal during a conversion. There are
two possible modes of operation, normal mode and power-down
mode. The point at which
CS is pulled high after the conversion
has been initiated will determine whether or not the AD7450 will
enter the power-down mode. Similarly, if already in power-down,
CS controls whether the device will return to normal operation or
remain in power-down. These modes of operation are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput rate
ratio for differing application requirements.
Normal Mode
This mode is intended for the fastest throughput rate perfor-
mance. The user does not have to worry about any power-up
times since the AD7450 is kept fully powered up. Figure 21
shows the general diagram of the operation of the AD7450 in
this mode. The conversion is initiated on the falling edge of
CS
as described in the Serial Interface section. To ensure the part
remains fully powered up,
CS must remain low until at least 10
SCLK falling edges have elapsed after the falling edge of
CS.
If
CS is brought high any time after the 10th SCLK falling edge,
but before the 16th SCLK falling edge, the part will remain
powered up, but the conversion will be terminated and SDATA
will go back into three-state.
Sixteen serial clock cycles are required to complete the conver-
sion and access the complete conversion result.
CS may idle
high until the next conversion or idle low until sometime prior
to the next conversion. Once a data transfer is complete, i.e.,
when SDATA has returned to three-state, another conversion
can be initiated after the quiet time, tQUIET, has elapsed by again
bringing
CS low.
10
16
SCLK
1
SDATA
CS
4 LEADING ZEROS AND CONVERSION RESULT
Figure 21. Normal Mode Operation
Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered down
between each conversion or a series of conversions may be
performed at a high throughput rate, during which the ADC is
powered down for a relatively long duration between these bursts of
several conversions. When the AD7450 is in the power-down
mode, all analog circuitry is powered down. To enter power-down
mode, the conversion process must be interrupted by bringing
CS
high anywhere after the second falling edge of SCLK and before
the 10th falling edge of SCLK as shown in Figure 22.
Rev. A
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