參數(shù)資料
型號(hào)： AD74322AARU
廠商： Analog Devices, Inc.
英文描述： Low Cost, Low Power Stereo Audio Analog Front End
中文描述： 低成本，低功耗立體聲音頻模擬前端
文件頁(yè)數(shù)： 9/20頁(yè)
文件大?。?/td> 123K
代理商： AD74322AARU
AD74322
–
9
–
ensures that all internal circuitry is reset and initialised to
PRELIMNARY TECHNICAL DATA
PRELMNARY
DATA
For f
SAMP
= 8 kHz, it is necessary to use the /3 setting in
Pre-Scaler 1, the /2 setting in Pre-Scaler 2 and pass
through in Pre-Scaler 3. T his results in an IMCLK =
8*10
3
* 256 = 2.048 MHz (= 12.288 MHz/6).
E xample 2: f
SAMP
= 48 kHz and 32 kHz required
MCLK = 24.576 MHz
For f
SAMP
= 48 kHz, it is necessary to use the /2 setting in
Pre-Scaler 1 and the /1 (pass-through) setting in Pre-
Scaler 2 and pass through in Pre-Scaler 3. T his results in
an IMCLK = 48*10
3
* 256 = 12.288 MHz.
For f
SAMP
= 32 kHz, it is necessary to use the /3 setting in
Pre-Scaler 1 and the /1 (pass-through) setting in Pre-
Scaler 2 and pass through in Pre-Scaler 3. T his results in
an IMCLK = 32*10
3
* 256 = 8.192 MHz.
E xample 3: fSAMP = 44.1 kHz and 11.025 kHz required
MCLK = 44.1*10
3
* 256 = 11.2896 MHz to cater for
44.1 kHz f
SAMP
For f
SAMP
= 11.025 kHz, it is necessary to use the /1 setting in Pre-
Scaler 1 and the /4 setting in Pre-Scaler 2 and pass
through in Pre-Scaler 3. T his results in an IMCLK =
11.025*10
3
* 256 = 2.8224 MHz (= 11.2896 MHz/4).
Sample Rates
For all applications the sampling rate is defined by the internal master
clock frequency (IMCLK) where IMCLK = 256 * f
SAMP
.
Power-On R eset
T he AD74322 features a power-on reset circuit which
TECHNCAL
4
DUAL
REGULATOR
DSP
AD743xx
FILTER
2.4 V
3.3 V
5.0 V
AVDD
VDD2
VDD1
AGND
DGND
DGND
DVDD
Figure <MCLK_Divider>
T he divider ratios will allow more convenient sample rate
selection from a common MCLK which may be required
in many voice related applications.
E xample 1: f
SAMP
= 48 kHz and 8 kHz required
MCLK = 48*10
3
* 256 = 12.288 MHz to cater for 48
kHz f
SAMP
Figure <PSU_Connection>
is also a software reset capability available by setting the
RESET bit in Control Register _. T his control register is
accessed through the Control Port.
Power Supplies and Grounds
T he AD74322 features three separate supplies: AVDD,
DVDD1 and DVDD2.
AVDD is the supply to the analog section of the device
and must therefore be of sufficient quality to preserve the
AD74322
’
s performance characteristics. It is nominally a
2.4 V supply.
DVDD1 is the supply for the digital interface section of
the device. It is fed from the digital supply voltage of the
DSP or controller to which the device is interfaced and
allows the AD74322 to interface with devices operating at
supplies of between 2.4 V -5% to 3.3 V + 10%.
DVDD2 is the supply for the digital core of the
AD74322. It is nominally a 2.4 V supply.
相關(guān)PDF資料
PDF描述
AD74322DAR Low Cost, Low Power Stereo Audio Analog Front End
AD74322 Low Cost, Low Power Stereo Audio Analog Front End
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD74322DAR 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost, Low Power Stereo Audio Analog Front End
AD74322DARU 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost, Low Power Stereo Audio Analog Front End
AD743AN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Operational Amplifier
AD743AQ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Operational Amplifier
AD743BN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Feedback Operational Amplifier
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