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參數(shù)資料
| 型號： | AD74322AARU |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Cost, Low Power Stereo Audio Analog Front End |
| 中文描述： | 低成本，低功耗立體聲音頻模擬前端 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大小： | 123K |
| 代理商： | AD74322AARU |
AD74322
–8–
Pr D 03/00
PRELIMNARY TECHNICAL DATA
DATA
TECHNCAL
Figure <Input_Swing>
F UNC T IONA L D E SC R IP T ION
ADC Section
T here are two ADC channels in the AD74322, configured as a stereo
pair. Each ADC channel can be independently muted. T he input pins
are switched between differential inputs or four single ended inputs
accordingly. The gain block can be programmed for independent left and
right gains, in steps of +3dB, from 0dB to +12dB. T he ADC operates at
an oversampling ratio of 128 and the decimation filter reduces the output
to the standard sample rates. T he output maximum
sample rate is 96 kHz at ASDAT A.
Automatic Level Control
Analog Sigma Delta Modulator
Decimator Section
T he digital decimation filter has a passband ripple of ±0.01dB and a
stopband attenuation of 70dB. T he filter is an FIR type with a linear
phase response. T he group delay at 48kHz is us. Output sample rates
up to 96 kHz are supported.
Input Signal swing
Each ADC input has an input range of 0.5 V
RMS
/ 1.414 V
P-P
(Single-
Ended) about a bias point equal to V
REFCAP
(See Figure
<Input_Swing>)
AD743xx
VINPx
VINNx
VREFCAP
1.414 V P-P
VREFCAP
1.414 V P-P
DAC Section
T he AD74322 has two DAC channels arranged as a stereo pair, with two,
fully differential voltage, analog outputs for improved noise and distortion
performance. Each channel has it
’
s own independently programmable
attenuator with a maximum attenuation of 63dB, adjustable in 1dB steps.
Digital inputs are via a serial data input pin and a common frame
(DLRCLK) and bit (DBLCK) clock or using a
‘
packed data
’
mode, both
channels can be input using a single data pin.
Interpolator Section
Digital Sigma Delta Modulator
DAC
Analog Output Filter
Output Signal swing
Each ADC input has an output range of 0.5 V
RMS
/ 1.414 V
P-P
(Single-
Ended) about a bias point equal to V
REFCAP
(See Figure
<Output_Swing>)
AD743xx
VOUTPx
VOUTNx
VREFCAP
1.414 V P-P
VREFCAP
1.414 V P-P
Figure <Output_Swing>
R eference
T he AD74322 features an on-chip reference whose
nominal value is 1.125 V.A __ nF capacitor applied at the
REFCAP pin is necessary to stabilise the referrence. (See
F igure <RE F C AP_Int>)
AD743xx
REFCAP
Figure <REFCAP_Int>
If it is required to use an external reference, because of its value or its
reference tempco, the internal reference can be disabled via Control
Register __ and the external reference applied at the REFCAP pin (See
Figure <REFCAP_Ext>).
EXTERNAL
REFERENCE
AD743xx
REFCAP
1.0 V
Figure <REFCAP_Ext>
Master Clocking Scheme
T he update rate of the AD74322
’
s ADC and DAC channels require an
internal master clock (IMCLK) which is 256 times that sample update
rate (IMCLK = 256 * F
S
). In order to provide some flexibility in
selecting sample rates, the device has a series of three
master clock pre-scalers which are programmable and
allow the user to choose a range of convenient sample
rates from a single external master clock. T he master
clock signal to the AD74322 is applied at the MCLK pin.
T he MCLK signal is passed through a series of two
programmable MC L K pre-scalers (divider) circuits which
can be selected to reduce the resulting Internal MCLK
(IMCLK ) frequency if required. T he first MCLK pre-
scaler provides divider ratios of /1 (pass through), /2, /3
while the second pre-scaler provides divider ratios of ./1
(pass through), /2, /4 and the third pre-scaler provides
ratios of /1 (pass through), /2 and /5..
MCLK
IMCLK
Programmable
MCLK
Divider
Control Reg
/1
/2
/3
/1
/2
/4
Pre-Scaler 1
Pre-Scaler 2
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| AD74322DARU | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost, Low Power Stereo Audio Analog Front End |
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