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參數(shù)資料
| 型號(hào)： | AD74322AARU |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Cost, Low Power Stereo Audio Analog Front End |
| 中文描述： | 低成本，低功耗立體聲音頻模擬前端 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 123K |
| 代理商： | AD74322AARU |
AD74322
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12
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Pr D 03/00
PRELIMNARY TECHNICAL DATA
PRELMNARY
DATA
TECHNCAL
LRCLK/SDIFS
SDOFS
DSDATA/SDI
BCLK/SCLK
ASDATA/SDO
AD743xx
(SLAVE)
TFS
DT
SCLK
DR
RFS
DSP
(
MASTER
)
Figure <Data_DSP_Master>
T he serial protocol uses a fixed position for data being sent to or received
from the Left and Right DACs and ADCs respectively and the control
words being sent to and the status words being received from the device
respectively. Figure <DSP_Protocol> details the arrangement of both
audio and control/status information in the serial transfer.
I
2
S
(Inter IC Sound Bus) Mode
T he I2S bus is a three line serial bus which features a serial data line
carrying both left and right (stereo) channels. T he Left and Right channel
information are selected by the status of the Left/Right Clock (Word
Select) line. Serial data is clocked by the Bit Clock line. Figures
<Data_I2S_DSP_Master> and <Data_I2S_DSP_Slave> detail the
interface configuration between controller and codec in I
2
S mode with
controller as master and slave respectively. Figure <> details I
2
S timing.
T he interface allows easy transfer of arbitrary length serial data samples
sent MSB first. T oggling of the Left/Right Clock line indicates that the
end of the current word will occur after the following Bit Clock cycle and
the start of the alternate channel word will occur on the subsequent Bit
Clock cycle
BCLK/
SCLK
LRCLK/
FS
DSDATA/
SDI
ASDATA/
SDO
CONTROL LEFT DAC RIGHT DAC
STATUS LEFT ADC RIGHT ADC
LRCLK/SDIFS
DSDATA/SDI
BCLK/SCLK
ASDATA/SDO
AD743xx
(SLAVE)
TFS
DT
TCLK
DR
RFS
ADSP-
21065L
(
MASTER
)
Figure <Data_I2S_DSP_Master>
LRCLK/SDIFS
DSDATA/SDI
BCLK/SCLK
ASDATA/SDO
AD743xx
(SLAVE)
TFS
DT
TCLK
DR
RFS
RCLK
ADSP-
21065L
(
MASTER
)
Figure <Data_I2S_DSP_Slave>
MSB
LSB
MSB
LSB
LRCLK
BCLK
SDATA
LEFT CHANNEL
RIGHT CHANNEL
I2S MODE - 16 TO 24-BITS PER CHANNEL
Figure <I2S_Timing>
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD74322DAR | Low Cost, Low Power Stereo Audio Analog Front End |
| AD74322 | Low Cost, Low Power Stereo Audio Analog Front End |
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| AD7441BRM | Pseudo Differential, 1MSPS, 12- |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD74322DAR | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost, Low Power Stereo Audio Analog Front End |
| AD74322DARU | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost, Low Power Stereo Audio Analog Front End |
| AD743AN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Operational Amplifier |
| AD743AQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Operational Amplifier |
| AD743BN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Feedback Operational Amplifier |
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