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參數(shù)資料
| 型號： | AD74322AARU |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Cost, Low Power Stereo Audio Analog Front End |
| 中文描述： | 低成本，低功耗立體聲音頻模擬前端 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大小： | 123K |
| 代理商： | AD74322AARU |
AD74322
–
11
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Pr D 03/00
PRELIMNARY TECHNICAL DATA
PRELMNARY
DATA
TECHNCAL
CDIN CLATCH CCLK CDOUT
INT E R F A C ING
The AD74322 features two separate interfaces, Control and Data, which
are used to program control settings and send/receive sample data
respectively. The Control interface is implemented using an SPI
type
protocol but transfers 16-bits per frame. T he Data interface uses either a
DSP or I
2
S
protocol to transfer stereo data samples between controller
and codec. T he DSP compatible interface mode allows data samples to be
transferred in a protocol that is supported by the serial interfaces of most
fixed- and floating-point DSPs.
In order to reduce peripheral requirements when interfacing the AD74322
with the host DSP, the DSP mode allows the DSP to send both data and
control information to the device via the data interface. T his is the default
mode and requires users to only use a single DSP SPORT to both control
the device and service it with data samples.
Control Interface
Control of the AD74322 operation is via a set of 16 Control Registers
which are programmed through the Control Port. The Control Port
protocol is similar to the SPI
ò
protocol with the exception that 16-bits of
data are transferred per frame. T he Control Port consists of the following
pins: CCLK - Control Port Serial Clock, CLAT CH - Control Port Latch
or Frame signal, CDIN - Control Port Serial Data In and CDOUT -
Control Port Data Out. CLAT CH is a framing signal that is active low.
When asserted, it gates the other interface lines as being active. CCLK is
used to clock input data on CDIN and clock output (readback) data on
CDOUT. Figure <Control_Interface> details the connectivity of the
Control Port to a controller and Figure <Control_Timing> details the
interface timing.
AD743xx
CONTROLLER
Figure <Control_Interface>
CLATCH
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
CCLK
CDIN
CDOUT
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
Figure <Control_Timing>
Data in and out of the Control Port go through a 16-bit
shift register whose contents are mapped to the internal
registers using the mapping scheme of Figure
<ContPortMap>. A 16-bit word received by the Control
Port is decoded as a read or write to a register address set
by bits 15 - 12. T his 4-bit register address selects 1 of 16
registers as shown in T able <ContRegMap>. Bit 11
selects whether a register read or write is requested -
Write = 0, Read = 1. Bit-10 is reserved. Bits 9 through 0
contain register data. Each Control register
’
s contents are
detailed below.
Data Interface
T here are two modes of operation of the data interface: DSP mode and
I2S mode. T he default mode of the data interface is a DSP mode which
the peripheral overhead required on the DSP when interfacing to the
AD74322. T his mode operates in a standard DSP serial format. In I2S
mode the data interface streams audio data samples being sent to or
received from the DACs and ADCs respectively, using the I2S serial
protocol.
In either mode it can be configured as either a master or slave device
ensuring connectivity to the largest number of host processors.
DSP Mode
The DSP mode allows interfacing to most fixed- and floating-point DSPs
as well as other processors such as RISCs etc that having serial ports that
DSP communications is that the serial data is framed by a separate Frame
Sync signal. Figures <Data_DSP_Slave> and <Data_DSP_Master> detail
connectivity in Master Mode (codec is master) and Slave Mode (codec is
slave) respectively.
LRCLK/SDIFS
SDOFS
DSDATA/SDI
BCLK/SCLK
ASDATA/SDO
AD743xx
(MASTER)
TFS
DT
SCLK
DR
RFS
DSP
(
SLAVE
)
Figure <Data_DSP_Slave>
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