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參數(shù)資料
| 型號： | AD74322AARU |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Cost, Low Power Stereo Audio Analog Front End |
| 中文描述： | 低成本，低功耗立體聲音頻模擬前端 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 123K |
| 代理商： | AD74322AARU |
AD74322
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15
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Pr D 03/00
PRELIMNARY TECHNICAL DATA
PRELMNARY
DATA
TECHNCAL
Clock and Latch signals. T he other method involves
creating a common Data In and Data Out buses where
each device has a common Clock but has separate Latch
signals which enable the devices on the bus at different
times - either as a T ime Division Multiplex (T DM) or
software control.
Daisy Chain Mode
In Daisy Chain Mode, the serial registers (16-bit) of each device are
cascaded together by connecting the controller
’
s Data Out to CDIN of
the first device and the CDOUT of the first device to
CDIN of the next device (see Figure
<C ontrol_C ascade_Daisy_C hain>). T he C DOUT of the
final device is connected to the controller
’
s Data In. T he
effective cascade length becomes 16 * N (where N is the
number of devices in cascade) and each control word write
to each device requires 16 * N CCLK cycles. Please note
that the CLAT CH pin of each device is driven from a
common controller output signal which must be active
during the entire 16 * N CCLK cycles as shown in Figure
<C ontrol_C ascade_T iming_D aisy_C hain>.
TDM Mode
In T DM Mode, each device
’
s CDIN and CDOUT are commoned to the
controller
’
s Data Out and Data In respectively (see Figure
<Control_Cascade_TDM>). Each device
’
s CLATCH pin is separately
controlled. When CLATCH is disasserted activity on CDIN and CCLK
is not recognised and the CDOUT pin is tri-stated. Figure
<Control_Cascade_Timing_TDM> shows TDM Mode Control timing.
D ata Port C ascading
T he Data Port of the AD74322 is designed to allow
multiple single or dual channel devices to be cascaded
from a single DSP or controller serial port (SPORT ).
T here is also a mode which allows stereo ADCs and
LRCLK/
SDIFS
SDOFS
DSDATA/
SDI
BCLK/
SCLK
ASDATA/
SDO
AD743xx
(SLAVE)
LRCLK/
SDIFS
SDOFS
DSDATA/
SDI
BCLK/
SCLK
ASDATA/
SDO
AD743xx
(SLAVE)
TFS
DT
SCLK
DR
RFS
DSP
(MASTER)
DACs (with I2S interfaces) to be interfaced to a cascade
of AD743xx devices. T his allows extra flexibility in
choosing the number of input and out channels in the
cascade. T he various (potential) modes for interfacing the
data ports of multiple devices are listed below:
DSP Mode - Daisy Chaining
In this mode, sample data is passed along a daisychain of
I/O registers in a similar manner that used in the present
AD733xx devices. At the sample event each ADC result is
placed in the I/O register and is subsequently shifted
towards the DSP
’
s Rx register. T his achieved by a
common SDIFS pulse which samples each device (enables
each device
’
s sample). {Drawback: as the device is stereo,
we would need to send 32 bits (or perhaps more) to the I/
O register at each sample event.}
TDM Mode
In multiplexed mode, each device is programmed with its cascade
position. T his allows devices to be enabled to the data buses only in their
appropriate time-slot as defined by the initial frame-sync
signal.
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| AD74322DAR | Low Cost, Low Power Stereo Audio Analog Front End |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD74322DAR | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost, Low Power Stereo Audio Analog Front End |
| AD74322DARU | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost, Low Power Stereo Audio Analog Front End |
| AD743AN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Operational Amplifier |
| AD743AQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Operational Amplifier |
| AD743BN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Feedback Operational Amplifier |
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