參數(shù)資料
型號(hào)： AD73360
廠商： Analog Devices, Inc.
英文描述： Six-Input Channel Analog Front End(通用6通道模擬輸入前端)
中文描述： 六輸入通道模擬前端（通用6通道模擬輸入前端）
文件頁(yè)數(shù)： 13/14頁(yè)
文件大小： 264K
代理商： AD73360
Preliminary Technical Data
AD73360
–13–
Prelim A1 02/98
Table XIII. Control Register A Description
CONTROL REGISTER A
Bit
Name
Description
0
1
2
3
4
5
6
7
DATA/
PGM
MM
DLB
SLB
DC0
DC1
DC2
RESET
Operating Mode (0 = Program; 1 = Data Mode)
Mixed Mode (0 = Off; 1 = Enabled)
Digital Loop-Back Mode (0 = Off; 1 = Enabled)
SPORT Loop-Back Mode (0 = Off; 1 = Enabled)
Device Count (Bit 0)
Device Count (Bit 1)
Device Count (Bit 2)
Software Reset (0 = Off; 1 = Initiates Reset)
Table XIV. Control Register B Description
CONTROL REGISTER B
Bit
Name
Description
0
1
2
3
4
5
6
7
DIR0
DIR1
SCD0
SCD1
MCD0
MCD1
MCD2
CEE
Decimation/Interpolation Rate (Bit 0)
Decimation/Interpolation Rate (Bit 1)
Serial Clock Divider (Bit 0)
Serial Clock Divider (Bit 1)
Master Clock Divider (Bit 0)
Master Clock Divider (Bit 1)
Master Clock Divider (Bit 2)
Control Echo Enable (0 = Off; 1 = Enabled)
Table XV. Control Register C Description
CONTROL REGISTER C
Bit
Name
Description
0
1
2
3
4
5
6
PU
Reserved
Reserved
Reserved
Reserved
PUREF
RU
Power-Up Device (0 = Power Down; 1 = Power On)
Must be programmed to zero (0)
Must be programmed to zero (0)
Must be programmed to zero (0)
Must be programmed to zero (0)
REF Power (0 = Power Down; 1 = Power On)
REFOUT Use (0 = Disable REFOUT; 1 = Enable
REFOUT)
Enable 5 V Operating Mode (0 = Disable 5 V Mode;
1 = Enable 5 V Mode)
7
5VEN
7
6
5
4
3
2
1
0
RESET
DC2
DC1
DC0
SLB
DLB
MM
DATA/
PGM
7
6
5
4
3
2
1
0
CEE
MCD2
MCD1
MCD0
SCD1
SCD0
DIR1
DIR0
7
6
5
4
3
2
1
0
5VEN
RU
PUREF
-
-
-
-
PU
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AD73360AR 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 5V 28-Pin SOIC W 制造商:Analog Devices 功能描述:IC 16-BIT ADC
AD73360AR-REEL 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 5V 28-Pin SOIC W T/R 制造商:Analog Devices 功能描述:AFE GEN PURPOSE 6ADC 16BIT 5V/5V/5V 28SOIC W - Tape and Reel
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