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參數(shù)資料
| 型號(hào)： | AD73360 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Six-Input Channel Analog Front End(通用6通道模擬輸入前端) |
| 中文描述： | 六輸入通道模擬前端（通用6通道模擬輸入前端） |
| 文件頁(yè)數(shù)： | 10/14頁(yè) |
| 文件大?。?/td> | 264K |
| 代理商： | AD73360 |
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Preliminary Technical Data
AD73360
–10–
Prelim A1 02/98
PIN FUNCTION DESCRIPTION
Mnemonic
Function
VINP1
VINN1
VINP2
VINN2
VINP3
VINN3
VINP4
VINN4
VINP5
VINN5
VINP6
VINN6
REFOUT
Analog Input to the Positive Terminal of Input Channel 1.
Analog Input to the Negative Terminal of Input Channel 1.
Analog Input to the Positive Terminal of Input Channel 2.
Analog Input to the Negative Terminal of Input Channel 2.
Analog Input to the Positive Terminal of Input Channel 3.
Analog Input to the Negative Terminal of Input Channel 3.
Analog Input to the Positive Terminal of Input Channel 4.
Analog Input to the Negative Terminal of Input Channel 4.
Analog Input to the Positive Terminal of Input Channel 5.
Analog Input to the Negative Terminal of Input Channel 5.
Analog Input to the Positive Terminal of Input Channel 6.
Analog Input to the Negative Terminal of Input Channel 6.
Buffered Reference Output, which has a nominal value of 1.2 V or 2.4 V, the value being dependent on the status
of Bit 5VEN (CRC:7).
A Bypass Capacitor to AGND2 of 0.1 μF is required for the on-chip reference. The capacitor should be fixed to
this pin.
Analog Power Supply Connection.
Analog Ground/Substrate Connection.
Digital Ground/Substrate Connection.
Digital Power Supply Connection.
Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing the digital
circuitry.
Output Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock data or
control information to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency
of the master clock (MCLK) divided by an integer number—this integer number being the product of the
external master clock rate divider and the serial clock rate divider.
Master Clock Input. MCLK is driven from an external clock signal.
Serial Data Output of the Codec. Both data and control information may be output on this pin and is clocked on
the positive edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is
low.
Framing Signal Output for SDO Serial Transfers. The frame sync is one-bit wide and it is active one SCLK
period before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK.
SDOFS is in three-state when SE is low.
Framing Signal Input for SDI Serial Transfers. The frame sync is one-bit wide and it is valid one SCLK
period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and
is ignored when SE is low.
Serial Data Input of the Codec. Both data and control information may be input on this pin and are clocked on
the negative edge of SCLK. SDI is ignored when SE is low.
SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins
of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to
decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are at
their original values (before SE was brought low), however the timing counters and other internal registers
are at their reset values.
Analog Ground Connection.
Analog Power Supply Connection.
REFCAP
AVDD2
AGND2
DGND
DVDD
RESET
SCLK
MCLK
SDO
SDOFS
SDIFS
SDI
SE
AGND1
AVDD1
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| AD73360AR | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 5V 28-Pin SOIC W 制造商:Analog Devices 功能描述:IC 16-BIT ADC |
| AD73360AR-REEL | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 5V 28-Pin SOIC W T/R 制造商:Analog Devices 功能描述:AFE GEN PURPOSE 6ADC 16BIT 5V/5V/5V 28SOIC W - Tape and Reel |
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| AD73360ARZ | 功能描述:IC PROCESSOR FRONTEND 6CH 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD73360ARZ | 制造商:Analog Devices 功能描述:ANALOG FRONT END 6 CH 28SOIC |
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