參數(shù)資料
型號(hào)： AD73311LARSZ-REEL7
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 26/36頁(yè)
文件大?。?/td> 0K
描述： IC PROCESSOR FRONT END LP 20SSOP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 16
通道數(shù)： 2
功率（瓦特）： 50mW
電壓 - 電源，模擬： 3V
電壓 - 電源，數(shù)字： 3V
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 20-SSOP
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： AD73311LARSZ-REEL7DKR
AD73311
–32–
REV. B
APPENDIX D
Configuring a Cascade of Two AD73311s to Operate in Mixed
Mode
This section describes a typical sequence of control words that
would be sent to a cascade of two AD73311s to configure them
for operation in mixed mode. It is not intended to be a definitive
initialization sequence, but will show users the typical input/
output events that occur in the programming and operation
phases
1. This description panel refers to Figure 36.
In Step 1, we have the first output sample event following device
reset. The SDOFS signal is raised on both devices simulta-
neously, which prepares the DSP Rx register to accept the ADC
word from Device 2 while SDOFS from Device 1 becomes an
SDIFS to Device 2. The cascade is configured as nonFSLB,
which means that the DSP has control over what is transmitted
to the cascade
2.
In Step 2, we observe the status of the devices following the
transmission of the first control word. The DSP has received the
ADC word from Device 2, while Device 2 has received the ADC
word from Device 1 and Device 1 has received the Control word
destined for Device 2. At this stage, the SDOFS of both devices
are again raised because Device 2 has received Device 1’s ADC
word and, as it is not addressed to Device 2, it is passed on to
the DSP. Likewise, Device 1 has received a control word des-
tined for Device 2—address field is not zero—and it decrements
the address field of the control word and passes it on.
Step 3 shows completion of the first series of control word
writes. The DSP has now received both ADC words and each
device has received a control word that addresses Control Regis-
ter A and sets the device count field equal to two devices and
programs the devices into Mixed Mode—MM and
PGM/DATA
set to one.
In Step 4, the next ADC sample event that happens raises the
SDOFS lines of each of the devices. The devices are in mixed
mode, which means that the serial port interrogates the MSB of
the 16-bit word sent to determine whether it contains DAC data
or control information. Following the programming of the device,
the ADC word in each device may need to be reconstructed
into mixed mode in Steps 1 to 3. This phenomenon also occurs
during mixed mode operation when a control word is written to
a device. The DSP Tx register contains the first of the two control
words to be written to the cascade—the word for Device 2.
In Step 5, following transmission of the first of the two control
words, the DSP Rx register contains Device 2’s ADC word,
Device 2’s serial register contains the Device 1 ADC word,
Device 1’s serial register contains the control word addressed to
Device 2, and the DSP Tx register contains the next control
word—that addressed to Device 1. Again, both devices raise
their SDOFS lines as both have received control words not
addressed to them.
Step 6 shows the completion of the second set of control word
writes. In this case both devices have received a control word
addressed to Control Register C which powers up the analog
sections of the devices. A control word is sent from the DSP’s
Tx register to read control register C of Device 2. This is done
to avoid corruption of the next ADC word
3.
In Step 7, the control word written to Device 2 is in Device 1,
and the DSP Tx register contains a control word to read Regis-
ter C of Device 1.
In Step 8, the control words implementing a read have been
received by both Devices 1 and 2. When the read bit in the
control word is recognized, it generates SDOFS pulses in both
devices to output the register data.
In Step 9, the read word from Device 2 has been transferred to
the DSP’s Rx register with its address field decremented. The
read word from Device 1 has been transferred to Device 2’s
serial register with its address field decremented. As this control
word in Device 2 does not have its address field at zero, it is not
addressing Device 2; it is shifted out of Device 2 following the
pulsing of the SDOFS line.
In Step 10, the readback is complete with the Device 1 read
word being transferred to the DSP’s Rx register. Note that its
address field has been further decremented.
Step 11 shows the next sample event. Note that the ADC values
are not corrupted due to the effects of the reads implemented in
steps 6–9.
The above example does not implement a DAC update but it is
possible to update the DACs and modify the control registers
within an ADC sampling interval providing the SCLK rate and
cascade length allows. DAC update uses the same frame sync
counting mechanism as detailed in the section on programming
a cascade for data mode operation
4.
NOTES
1This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are
enabled. It is important to ensure there is no latency (separation) between
control words in a cascade configuration. This is especially the case when
programming Control Register B, as it contains settings for SCLK and
DMCLK rates.
2In mixed mode it is possible to transmit both DAC and control words to the
devices in a cascade. If FSLB is used, the number of words sent to the cascade
equals the number of devices in the cascade, which means that DAC updates
may need to be substituted with a register write. In nonFSLB, the DSP can
send extra control words if necessary and if there is sufficient time before the
next sample event.
3In mixed mode, it may be necessary to terminate a control word write to a
device with a control word read to that device in order to ensure that the next
ADC sample is correct. Alternatively the ADC word can either be discarded or,
if this is not possible, be rebuilt by incrementing the “address field” within the
16-bit word.
4In mixed mode, DAC update is done using the same SDIFS counting scheme
as in normal data mode with the exception that only DAC words (MSB set to
zero) are recognized as being able to increment the frame sync counters.
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