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參數(shù)資料
| 型號： | AD73311LARSZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR FRONT END LP 20SSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 2 |
| 功率（瓦特）： | 50mW |
| 電壓 - 電源，模擬： | 3V |
| 電壓 - 電源，數(shù)字： | 3V |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD73311LARSZ-REEL7DKR |
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AD73311
–10–
REV. B
PIN FUNCTION DESCRIPTIONS
Pin
Number
Mnemonic
Function
1
VOUTP
Analog Output from the Positive Terminal of the Output Channel.
2
VOUTN
Analog Output from the Negative Terminal of the Output Channel.
3
AVDD1
Analog Power Supply Connection for the Output Driver.
4
AGND1
Analog Ground Connection for the Output Driver.
5
VINP
Analog Input to the Positive Terminal of the Input Channel.
6
VINN
Analog Input to the Negative Terminal of the Input Channel.
7
REFOUT
Buffered Reference Output, which has a nominal value of 1.2 V or 2.4 V, the value being dependent
on the status of Bit 5VEN (CRC:7).
8
REFCAP
A Bypass Capacitor to AGND2 of 0.1
F is required for the on-chip reference. The capacitor should
be fixed to this pin.
9
AVDD2
Analog Power Supply Connection.
10
AGND2
Analog Ground/Substrate Connection.
11
DGND
Digital Ground/Substrate Connection.
12
DVDD
Digital Power Supply Connection.
13
RESET
Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing
the digital circuitry.
14
SCLK
Output Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock
data or control information to and from the serial port (SPORT). The frequency of SCLK is equal to
the frequency of the master clock (MCLK) divided by an integer number—this integer number being
the product of the external master clock rate divider and the serial clock rate divider.
15
MCLK
Master Clock Input. MCLK is driven from an external clock signal.
16
SDO
Serial Data Output of the Codec. Both data and control information may be output on this pin and is
clocked on the positive edge of SCLK. SDO is in three-state when no information is being transmitted
and when SE is low.
17
SDOFS
Framing Signal Output for SDO Serial Transfers. The frame sync is one-bit wide and it is active one
SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the positive
edge of SCLK. SDOFS is in three-state when SE is low.
18
SDIFS
Framing Signal Input for SDI Serial Transfers. The frame sync is one-bit wide and it is valid one
SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of
SCLK and is ignored when SE is low.
19
SDI
Serial Data Input of the Codec. Both data and control information may be input on this pin and are
clocked on the negative edge of SCLK. SDI is ignored when SE is low.
20
SE
SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the
output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled
internally in order to decrease power dissipation. When SE is brought high, the control and data regis-
ters of the SPORT are at their original values (before SE was brought low), however the timing
counters and other internal registers are at their reset values.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD73311LARU | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin TSSOP |
| AD73311LARU-REEL | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin TSSOP T/R |
| AD73311LARU-REEL7 | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin TSSOP T/R |
| AD73311LARUZ | 功能描述:IC PROCESSOR FRONT END LP 20SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD73311LARUZ-RL | 功能描述:IC PROCESSOR FRONT END LP 20SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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